Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems

We present a hierarchical address-event routing (HiAER) architecture for scalable communication of neural and synaptic spike events between neuromorphic processors, implemented with five Xilinx Spartan-6 field-programmable gate arrays and four custom analog neuromophic integrated circuits serving 262k neurons and 262M synapses. The architecture extends the single-bus address-event representation protocol to a hierarchy of multiple nested buses, routing events across increasing scales of spatial distance. The HiAER protocol provides individually programmable axonal delay in addition to strength for each synapse, lending itself toward biologically plausible neural network architectures, and scales across a range of hierarchies suitable for multichip and multiboard systems in reconfigurable large-scale neuromorphic systems. We show approximately linear scaling of net global synaptic event throughput with number of routing nodes in the network, at $3.6\times 10^{7}$ synaptic events per second per 16k-neuron node in the hierarchy.

[1]  André van Schaik,et al.  An aVLSI programmable axonal delay circuit with spike timing dependent delay adaptation , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[2]  Gert Cauwenberghs,et al.  Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons , 2001, Neural Networks.

[3]  Giacomo Indiveri,et al.  Exploiting device mismatch in neuromorphic VLSI systems to implement axonal delays , 2012, The 2012 International Joint Conference on Neural Networks (IJCNN).

[4]  André van Schaik,et al.  AER EAR: A Matched Silicon Cochlea Pair With Address Event Representation Interface , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Hsien-Hsin S. Lee,et al.  3D-MAPS: 3D Massively parallel processor with stacked memory , 2012, 2012 IEEE International Solid-State Circuits Conference.

[6]  Johannes Schemmel,et al.  A VLSI Implementation of the Adaptive Exponential Integrate-and-Fire Neuron Model , 2010, NIPS.

[7]  Gert Cauwenberghs,et al.  Reverse engineering the cognitive brain , 2013, Proceedings of the National Academy of Sciences.

[8]  Massimo A. Sivilotti,et al.  Wiring considerations in analog VLSI systems, with application to field-programmable networks , 1992 .

[9]  Johannes Schemmel,et al.  Realizing biological spiking network models in a configurable wafer-scale hardware system , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[10]  Misha Anne Mahowald,et al.  VLSI analogs of neuronal visual processing: a synthesis of form and function , 1992 .

[11]  Rodrigo Alvarez-Icaza,et al.  A Multicast Tree Router for Multichip Neuromorphic Systems , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Johannes Schemmel,et al.  Stochastic inference with deterministic spiking neurons , 2013, ArXiv.

[13]  Craig T. Jin,et al.  An Address-Event Vision Sensor for Multiple Transient Object Detection , 2007, IEEE Transactions on Biomedical Circuits and Systems.

[14]  Jennifer Hasler,et al.  Neuron Array With Plastic Synapses and Programmable Dendrites , 2013, IEEE Transactions on Biomedical Circuits and Systems.

[15]  Kwabena Boahen,et al.  Point-to-point connectivity between neuromorphic chips using address events , 2000 .

[16]  Dharmendra S. Modha,et al.  A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[17]  John Lazzaro.  Temporal Adaptation in a Silicon Auditory Nerve , 1991, NIPS.

[18]  Tobi Delbrück,et al.  CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory–Processing– Learning–Actuating System for High-Speed Visual Object Recognition and Tracking , 2009, IEEE Transactions on Neural Networks.

[19]  P. Lennie.  The Cost of Cortical Computation , 2003, Current Biology.

[20]  Bertram E. Shi,et al.  Expandable Networks for Neuromorphic Chips , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  S. Laughlin,et al.  An Energy Budget for Signaling in the Grey Matter of the Brain , 2001, Journal of cerebral blood flow and metabolism : official journal of the International Society of Cerebral Blood Flow and Metabolism.

[22]  G. Shepherd.  The Synaptic Organization of the Brain , 1979 .

[23]  Stephan Hartmann,et al.  VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality , 2011, Front. Neurosci..

[24]  Terrence J. Sejnowski,et al.  The Computational Brain , 1996, Artif. Intell..

[25]  Luis A. Plana,et al.  SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[26]  John Wawrzynek,et al.  Silicon Auditory Processors as Computer Peripherals , 1992, NIPS.

[27]  Gert Cauwenberghs,et al.  Spike Timing-Dependent Plasticity in the Address Domain , 2002, NIPS.

[28]  Shih-Chii Liu,et al.  Temporal coding in a silicon network of integrate-and-fire neurons , 2004, IEEE Transactions on Neural Networks.

[29]  Andrew S. Cassidy,et al.  A million spiking-neuron integrated circuit with a scalable communication network and interface , 2014, Science.

[30]  Giacomo Indiveri,et al.  A reconfigurable neuromorphic VLSI multi-chip system applied to visual motion computation , 1999, Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems.

[31]  W. Precht.  The synaptic organization of the brain G.M. Shepherd, Oxford University Press (1975). 364 pp., £3.80 (paperback) , 1976, Neuroscience.

[32]  Frank C. Hoppensteadt,et al.  Polychronous Wavefront Computations , 2009, Int. J. Bifurc. Chaos.

[33]  Bernabé Linares-Barranco,et al.  A 128$\,\times$ 128 1.5% Contrast Sensitivity 0.9% FPN 3 µs Latency 4 mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Preamplifiers , 2013, IEEE Journal of Solid-State Circuits.

[34]  J. Little.  A Proof for the Queuing Formula: L = λW , 1961 .

[35]  Kwabena Boahen,et al.  An in-silico Neural Model of Dynamic Routing through Neuronal Coherence , 2007, NIPS.

[36]  Jongkil Park,et al.  Live demonstration: Hierarchical Address-Event Routing architecture for reconfigurable large scale neuromorphic systems , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[37]  Misha A. Mahowald,et al.  An Analog VLSI System for Stereoscopic Vision , 1994 .

[38]  Olivier Temam,et al.  Configurable conduction delay circuits for high spiking rates , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[39]  René Schüffny,et al.  Analyzing the Scaling of Connectivity in Neuromorphic Hardware and in Models of Neural Networks , 2011, IEEE Transactions on Neural Networks.

[40]  Gert Cauwenberghs,et al.  Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses , 2007, IEEE Transactions on Neural Networks.

[41]  Alan F. Murray,et al.  Large Developing Receptive Fields Using a Distributed and Locally Reprogrammable Address–Event Receiver , 2010, IEEE Transactions on Neural Networks.

[42]  Andreas G. Andreou,et al.  A Contrast Sensitive Silicon Retina with Reciprocal Synapses , 1991, NIPS.

[43]  Dharmendra S. Modha,et al.  A Digital Neurosynaptic Core Using Event-Driven QDI Circuits , 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.

[44]  Travis A. Jarrell,et al.  The Connectome of a Decision-Making Neural Network , 2012, Science.

[45]  T. Delbruck,et al.  > Replace This Line with Your Paper Identification Number (double-click Here to Edit) < 1 , 2022 .

[46]  Timothy E. J. Behrens,et al.  Human connectomics , 2012, Current Opinion in Neurobiology.

[47]  Vipin Kumar,et al.  A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs , 1998, SIAM J. Sci. Comput..

[48]  A M Dale,et al.  Measuring the thickness of the human cerebral cortex from magnetic resonance images. , 2000, Proceedings of the National Academy of Sciences of the United States of America.

[49]  Philipp Häfliger,et al.  High-Speed Serial AER on FPGA , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[50]  Gert Cauwenberghs,et al.  Event-driven contrastive divergence for spiking neuromorphic systems , 2013, Front. Neurosci..

[51]  Eugenio Culurciello,et al.  An Address-Event Fall Detector for Assisted Living Applications , 2008, IEEE Transactions on Biomedical Circuits and Systems.

[52]  Bernabé Linares-Barranco,et al.  A ${0.35}~\mu{\rm m}$ Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links , 2012, IEEE Transactions on Biomedical Circuits and Systems.

[53]  S. Joshi,et al.  65k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing , 2012, 2012 IEEE Biomedical Circuits and Systems Conference (BioCAS).

[54]  Giacomo Indiveri,et al.  Synthesizing cognition in neuromorphic electronic systems , 2013, Proceedings of the National Academy of Sciences.

[55]  Rodrigo Alvarez-Icaza,et al.  Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations , 2014, Proceedings of the IEEE.

[56]  Bernabé Linares-Barranco,et al.  Fast Vision Through Frameless Event-Based Sensing and Convolutional Processing: Application to Texture Recognition , 2010, IEEE Transactions on Neural Networks.

[57]  Jim D. Garside,et al.  SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation , 2013, IEEE Journal of Solid-State Circuits.

[58]  Tobi Delbrück,et al.  A 128$\times$ 128 120 dB 15 $\mu$s Latency Asynchronous Temporal Contrast Vision Sensor , 2008, IEEE Journal of Solid-State Circuits.

[59]  Young-Hyun Jun,et al.  8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.

[60]  Narayanan Vijaykrishnan,et al.  A framework for accelerating neuromorphic-vision algorithms on FPGAs , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[61]  S. Joshi,et al.  Scalable event routing in hierarchical neural array architecture with global synaptic connectivity , 2010, 2010 12th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2010).

[62]  Jongkil Park,et al.  Event-driven neural integration and synchronicity in analog VLSI , 2012, 2012 Annual International Conference of the IEEE Engineering in Medicine and Biology Society.

[63]  Bernabé Linares-Barranco,et al.  Multicasting Mesh AER: A Scalable Assembly Approach for Reconfigurable Neuromorphic Structured AER Systems. Application to ConvNets , 2013, IEEE Transactions on Biomedical Circuits and Systems.

[64]  Giacomo Indiveri,et al.  A serial communication infrastructure for multi-chip address event systems , 2008, 2008 IEEE International Symposium on Circuits and Systems.