In our prior study of an <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {L}$ </tex-math></inline-formula>-bit priority encoder (PE), a so-called one-directional-array to two-directional-array conversion method is deployed to turn an <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {L}$ </tex-math></inline-formula>-bit input data into an <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {M\times N}$ </tex-math></inline-formula>-bit matrix. Following this, an <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {N}$ </tex-math></inline-formula>-bit PE and an <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {M}$ </tex-math></inline-formula>-bit PE are employed to obtain a row index and column index. From those, the highest priority bit of <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {L}$ </tex-math></inline-formula>-bit input data is achieved. This brief extends our previous work to construct a scalable architecture of high-performance large-sized PEs. An optimum pair of (<inline-formula> <tex-math notation="LaTeX">$\boldsymbol {M}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {N}$ </tex-math></inline-formula>) and look-ahead signal are proposed to improve the overall PE performance significantly. The evaluation is achieved by implementing a variety of PEs whose <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {L}$ </tex-math></inline-formula> varies from 4-bit to 4096-bit in 180-nm CMOS technology. According to post-place-and-route simulation results, at PE size of 64 bits, 256 bits, and 2048 bits the operating frequencies reach 649 MHz, 520 MHz, and 370 MHz, which are 1.2 times, 1.5 times, and 1.4 times, as high as state-of-the-art ones.
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