Inter-procedural resource sharing in High Level Synthesis through function proxies

Modular design is becoming increasingly important in High Level Synthesis (HLS) flows. Current HLS flows generate hierarchical and modular designs that mimic the structure and call graph of the input specification by translating functions into modules. Function calls are translated by instantiating the callee module in the data-path of its caller, allowing for resource sharing when the same function is called multiple times. However, if two different callers invoke the same function, current HLS flows cannot share the instance of the module between the two callers, even if they invoke the function in a mutually exclusive way. In this paper, we propose a methodology that enables sharing of (sub)modules across modules boundaries. Sharing is obtained through function proxies, which act as forwarders of function calls in the original specification to shared modules without reducing performance. Building on the concept of function proxies, we propose a methodology and the related components to perform HLS of function calls through function pointers, without requiring complete static knowledge of the alias set (point-to set). We show that module sharing through function proxies provides valuable area savings and no significant impacts on the execution delays, and that our synthesis approach for function pointers enables dynamic polymorphism.

[1]  Hiroyuki Tomiyama,et al.  Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis , 2009, J. Inf. Process..

[2]  Frank Vahid Partitioning sequential programs for CAD using a three-step approach , 2002, TODE.

[3]  Giovanni De Micheli,et al.  Synthesis of hardware models in C with pointers and complex data structures , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Abir Awad Abir Awad , 2022 .

[5]  Ahmed Amine Jerraya,et al.  Behavioral Synthesis and Component Reuse with VHDL , 1996 .

[6]  Seon Wook Kim,et al.  GCC2verilog compiler toolset for complete translation of c programming language into verilog HDL , 2011 .

[7]  Giovanni De Micheli,et al.  Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Jason Cong,et al.  Pattern-based behavior synthesis for FPGA resource reduction , 2008, FPGA '08.

[9]  Antônio Augusto Fröhlich,et al.  Toward Unified Design of Hardware and Software Components Using C++ , 2014, IEEE Trans. Computers.

[10]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[11]  Fabrizio Ferrandi,et al.  Code transformations based on speculative SDC scheduling , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[12]  Jason Helge Anderson,et al.  LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems , 2013, TECS.

[13]  Seon Wook Kim,et al.  Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architecture , 2011, Microprocess. Microsystems.

[14]  Frank Vahid Procedure exlining: a transformation for improved system and behavioral synthesis , 1995 .

[15]  Hiroyuki Tomiyama,et al.  Function Call Optimization for Efficient Behavioral Synthesis , 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[16]  Christian Haubelt,et al.  Hardware synthesis of recursive functions through partial stream rewriting , 2012, DAC Design Automation Conference 2012.

[17]  Tom Feist,et al.  Vivado Design Suite , 2012 .

[18]  Daniel D. Gajski,et al.  Clustering for improved system-level functional partitioning , 1995 .