Upper bounding fault coverage by structural analysis and signal monitoring

A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, certain signal conditions are monitored during logic simulation. These signal conditions are specified by an analysis of dominators and signal reconvergences in the circuit graph. After simulation, a post-processing step identifies faults that cannot be detected by the sequence. For combinational IS GAS benchmarks, the runtime overhead for the algorithm is found to be around 30-40% over that of a logic simulator. Experimental data show a substantial reduction of error in statistical estimates obtained by a stuck-fault coverage estimator when corrected for faults found by this algorithm as guaranteed to be undetected by the given sequence. An effective application of this technique is demonstrated for scan-based test point selection in an industrial scenario where circuit size and vector length prohibit the use of fault simulation

[1]  D. Pradhan,et al.  Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization , 2003 .

[2]  P. R. Menon,et al.  Critical Path Tracing: An Alternative to Fault Simulation , 1984, IEEE Des. Test.

[3]  Sungju Park,et al.  Why is less information from logic simulation more useful in fault simulation? , 1990, Proceedings. International Test Conference 1990.

[4]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[6]  Dhiraj K. Pradhan,et al.  Accelerated dynamic learning for test pattern generation in combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Sunil Jain,et al.  Statistical Fault Analysis , 1985, IEEE Design & Test of Computers.

[8]  Dhiraj K. Pradhan,et al.  Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization , 1994, The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003..

[9]  Alfred V. Aho,et al.  The Design and Analysis of Computer Algorithms , 1974 .

[10]  M. Ray Mercer,et al.  A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.