A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters

Testing high-speed A/D converters for dynamic specifications needs test equipment running at high frequency. In this paper, a methodology to test high-speed A/D converters using low-frequency resources is described. It is based on the alternate testing approach. In the proposed methodology, models are built to map the signatures of an initial set of devices, obtained on the proposed low-cost test set-up, to the dynamic specifications of the same devices, obtained using high-precision test equipment. During production testing, the devices are tested on the low-cost test set-up. The dynamic specifications of the devices are estimated by capturing their signatures on the low cost test set-up and processing them with the pre-developed models. As opposed to the conventional method of dynamic specification testing of data converters, the proposed approach does not require the tester resources running at a frequency higher than the device-under-test (DUT). The test methodology was verified in simulations as well as in hardware with specification estimation error of less than 5%.

[1]  Giovanni Chiorboli Sub-picosecond aperture uncertainty measurements , 2001, IMTC 2001. Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No.01CH 37188).

[2]  Joseph A. Mielke Frequency Domain Testing of ADCs , 1996, IEEE Des. Test Comput..

[3]  D. A. McLeod Dynamic testing of analogue to digital converters , 1991 .

[4]  J. Schoukens,et al.  Creating spectrally pure signals for adc-testing , 2003, Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412).

[5]  Sebastian Sattler,et al.  Controlled sine wave fitting for ADC test , 2004 .

[6]  Abhijit Chatterjee,et al.  System-level testing of RF transmitter specifications using optimized periodic bitstreams , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[7]  B. N. Suresh Babu,et al.  Testing an ADC linearized with pseudorandom dither , 1998, IEEE Trans. Instrum. Meas..

[8]  Stephen K. Sunter,et al.  A simplified polynomial-fitting algorithm for DAC and ADC BIST , 1997, Proceedings International Test Conference 1997.

[9]  M. Wagdy,et al.  Linearizing average transfer characteristics of ideal ADC's via analog and digital dither , 1994 .

[10]  Abhijit Chatterjee,et al.  Reconfiguration for enhanced alternate test (REALTest) of analog circuits , 2004, 13th Asian Test Symposium.

[11]  Shalabh Goyal,et al.  Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost Tester , 2005, 14th Asian Test Symposium (ATS'05).

[12]  T. E. Linnenbrink,et al.  ADC testing with IEEE Std 1241-2000 , 2001, IMTC 2001. Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No.01CH 37188).

[13]  J. Friedman Multivariate adaptive regression splines , 1990 .

[14]  M. F. Wagdy,et al.  Determining ADC effective number of bits via histogram testing , 1991 .

[15]  Abhijit Chatterjee,et al.  Automatic multitone alternate test-generaton for rf circuits using behavioral models , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[16]  Kwang-Ting Cheng,et al.  A BIST scheme for on-chip ADC and DAC testing , 2000, DATE '00.

[17]  Jerome H. Friedman Multivariate adaptive regression splines (with discussion) , 1991 .

[18]  Abhijit Chatterjee,et al.  Prediction of analog performance parameters using fast transienttesting , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Giovanni Chiorboli Sub-picosecond aperture-uncertainty measurements [ADCs] , 2002, IEEE Trans. Instrum. Meas..

[20]  S. Pei,et al.  The effect of noise in dynamic testing of A/D converters , 1992, [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems.

[21]  Jeffrey K. Hollingsworth,et al.  Instrumentation and Measurement , 1998, 2022 International Symposium on Electronics and Telecommunications (ISETC).

[22]  Mohamad Sawan,et al.  On chip testing data converters using static parameters , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[23]  Ling Ming,et al.  A complete BIST scheme for ADC linearity testing , 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

[24]  Kuen-Jong Lee,et al.  An on chip ADC test structure , 2000, DATE '00.

[25]  Daniel Bloyet,et al.  Measurement of timing jitter contributions in a dynamic test setup for A/D converters , 2001, IEEE Trans. Instrum. Meas..