Design and Implementation of First-in First-out Memory

Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala.

[1]  Cheng-Shang Chang,et al.  Using switched delay lines for exact emulation of FIFO multiplexers with variable length bursts , 2006, IEEE Journal on Selected Areas in Communications.

[2]  H. Wang,et al.  Double-edge-triggered address pointer for low-power high-speed FIFO memories , 1997 .

[3]  Edward A. Lee,et al.  Multidimensional synchronous dataflow , 2002, IEEE Trans. Signal Process..

[4]  Razak Hossain,et al.  Low power design using double edge triggered flip-flops , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Ivan E. Sutherland,et al.  GasP: a minimal FIFO control , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.

[6]  Andrea Fumagalli,et al.  Multibuffer delay line architectures for efficient contention resolution in optical switching nodes , 2000, IEEE Trans. Commun..

[7]  Hendrikus J. M. Veendrick,et al.  The behaviour of flip-flops used as synchronizers and prediction of their failure rate , 1980 .

[8]  Wolfgang Fichtner,et al.  Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[9]  Dhabaleswar K. Panda,et al.  HIPIQS: A High-Performance Switch Architecture Using Input Queuing , 2002, IEEE Trans. Parallel Distributed Syst..

[10]  Yuanyuan Yang,et al.  Multicast scheduling in WDM switching networks , 2003, IEEE International Conference on Communications, 2003. ICC '03..

[11]  Steven M. Nowick,et al.  Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools , 2001 .

[12]  N. Kanopoulos,et al.  A first-in, first-out memory for signal processing applications , 1986 .

[13]  H. Fujiwara,et al.  A 20-ns 256 K*4 FIFO memory , 1988 .

[14]  Nobutaro Shibata,et al.  A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell , 2002 .