Power Gating Design Automation

[1]  Kimiyoshi Usami,et al.  Automated selective multi-threshold design for ultra-low standby applications , 2002, ISLPED '02.

[2]  C. Pacha,et al.  Efficiency of body biasing in 90-nm CMOS for low-power digital circuits , 2004, IEEE Journal of Solid-State Circuits.

[3]  Anantha Chandrakasan,et al.  MTCMOS hierarchical sizing based on mutual exclusive discharge patterns , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[4]  Kaushik Roy,et al.  Intrinsic leakage in low power deep submicron CMOS ICs , 1997, Proceedings International Test Conference 1997.

[5]  T. Sakurai,et al.  Optimal zigzag (OZ): an effective yet feasible power-gating scheme achieving two orders of magnitude lower standby leakage , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[6]  Takeshi Kitahara,et al.  Area-efficient selective multi-threshold CMOS design methodology for standby leakage power reduction , 2005, Design, Automation and Test in Europe.

[7]  Rajendran Panda,et al.  Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing , 1999, DAC '99.

[8]  H. Kawaguchi,et al.  Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[9]  Mohamed I. Elmasry,et al.  Design and optimization of multithreshold CMOS (MTCMOS) circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[11]  S. Borkar,et al.  Dynamic-sleep transistor and body bias for active leakage power control of microprocessors , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[12]  Sarma B. K. Vrudhula,et al.  Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Jeong-Taek Kong,et al.  An MTCMOS design methodology and its application to mobile computing , 2003, ISLPED '03.

[14]  Michael Immediato,et al.  Enchanced multi-threshold (MTCMOS) circuits using variable well bias , 2001, ISLPED '01.

[15]  T. Ghani,et al.  Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[16]  Mark C. Johnson,et al.  Design and optimization of low voltage high performance dual threshold CMOS circuits , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[17]  Benton H. Calhoun,et al.  Power Gating and Dynamic Voltage Scaling , 2006 .

[18]  J. Wang,et al.  A highly-integrated 3G CDMA2000 1X cellular baseband chip with GSM/AMPS/GPS/Bluetooth/multimedia capabilities and ZIF RIF support , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[19]  T. Sakurai,et al.  A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current , 2000, IEEE Journal of Solid-State Circuits.

[20]  A.P. Chandrakasan,et al.  A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[21]  Trevor Mudge,et al.  Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads , 2002, ICCAD 2002.