Evaluation of a Commercial Microprocessor

A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate Division of the University of California, Berkeley.

[1]  Ruby B. Lee Realtime MPEG video via software decompression on a PA-RISC processor , 1995, Digest of Papers. COMPCON'95. Technologies for the Information Superhighway.

[2]  Ruby B. Lee,et al.  64-bit and multimedia extensions in the PA-RISC 2.0 architecture , 1996, COMPCON '96. Technologies for the Information Superhighway Digest of Papers.

[3]  Joan L. Mitchell,et al.  MPEG Video Compression Standard , 1996, Springer US.

[4]  Rachel Yung Design decisions influencing the UltraSPARC's instruction fetch architecture , 1996, Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29.

[5]  W. Chen,et al.  Native signal processing on the Ultrasparc in the Ptolemy environment , 1996, Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers.

[6]  R. M. Tomasulo,et al.  An efficient algorithm for exploiting multiple arithmetic units , 1995 .

[7]  M. Carter Computer graphics: Principles and practice , 1997 .

[8]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[9]  Marc Tremblay,et al.  The visual instruction set (VIS) in UltraSPARC , 1995, Digest of Papers. COMPCON'95. Technologies for the Information Superhighway.

[10]  Don Rice,et al.  High-performance image processing using special-purpose cpu instructions: the ultrasparc visual inst , 1996 .

[11]  Sam Harrell,et al.  The national technology roadmap for semiconductors and SEMATECH future directions , 1996 .

[12]  Wei Ding,et al.  VIS-based native video processing on UltraSPARC , 1996, Proceedings of 3rd IEEE International Conference on Image Processing.

[13]  James Gateley UltraSPARC™ -I Emulation , 1995, DAC 1995.

[14]  Marc Tremblay,et al.  UltraSPARC: the next generation superscalar 64-bit SPARC , 1995, Digest of Papers. COMPCON'95. Technologies for the Information Superhighway.

[15]  장훈,et al.  [서평]「Computer Organization and Design, The Hardware/Software Interface」 , 1997 .

[16]  Norman P. Jouppi,et al.  Available instruction-level parallelism for superscalar and superpipelined machines , 1989, ASPLOS III.

[17]  Corporate SPARC architecture manual - version 8 , 1992 .

[18]  Marc Tremblay,et al.  A three dimensional register file for superscalar processors , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

[19]  Michael Kagan,et al.  The Pentium(R) processor with MMX/sup TM/ technology , 1997, Proceedings IEEE COMPCON 97. Digest of Papers.

[20]  Alvin M. Despain,et al.  The 16-fold way: a microparallel taxonomy , 1993, MICRO.

[21]  David Gao,et al.  System design methodology of ultraSPARC-I , 1995, DAC '95.

[22]  David Keppel,et al.  Shade: a fast instruction-set simulator for execution profiling , 1994, SIGMETRICS.

[23]  N. O V E M B,et al.  Digital, MIPS Add Multimedia Extensions: 11/18/96 , 1996 .

[24]  David W. Wall,et al.  Limits of instruction-level parallelism , 1991, ASPLOS IV.

[25]  Uri C. Weiser,et al.  MMX technology extension to the Intel architecture , 1996, IEEE Micro.

[26]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[27]  Trevor N. Mudge,et al.  Correlation and Aliasing in Dynamic Branch Predictors , 1996, ISCA.

[28]  Michael J. Flynn,et al.  Some Computer Organizations and Their Effectiveness , 1972, IEEE Transactions on Computers.

[29]  Klara Nahrstedt,et al.  Multimedia: Computing, Communications and Applications , 1994 .

[30]  Robert Yung Design decisions influencing the UltraSPARC's instruction fetch architecture , 1996, MICRO.

[31]  MI CRO OSSOR MIPS R10000 Uses Decoupled Architecture: 10/24/94 , 1994 .

[32]  J A Fisher,et al.  Instruction-Level Parallel Processing , 1991, Science.

[33]  Leslie Kohn,et al.  MPEG video decoding with the UltraSPARC visual instruction set , 1995, Digest of Papers. COMPCON'95. Technologies for the Information Superhighway.

[34]  Mark D. Hill,et al.  A case for direct-mapped caches , 1988, Computer.

[35]  Paul Tucker,et al.  Hewlett-Packard's new multimedia enabled PA-RISC workstations , 1994, Proceedings of COMPCON '94.

[36]  Wen-Mei William Hwu,et al.  Hpsm: exploiting concurrency to achieve high performance in a single-chip microarchitecture , 1987 .

[37]  DeForest Tovey,et al.  Microarchitecture of HaL's CPU , 1995, Digest of Papers. COMPCON'95. Technologies for the Information Superhighway.

[38]  Roy L. Russo,et al.  On a Pin Versus Block Relationship For Partitions of Logic Graphs , 1971, IEEE Transactions on Computers.

[39]  C. K. Yuen,et al.  Theory and Application of Digital Signal Processing , 1978, IEEE Transactions on Systems, Man, and Cybernetics.

[40]  Joan L. Mitchell,et al.  JPEG: Still Image Data Compression Standard , 1992 .

[41]  Carlo H. Séquin,et al.  A VLSI RISC , 1982, Computer.

[42]  Neil C. Wilhelm,et al.  Caching processor general registers , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[43]  Uri C. Weiser,et al.  Intel's MMX/sup TM/ technology-a new instruction set extension , 1997, Proceedings IEEE COMPCON 97. Digest of Papers.

[44]  박치항,et al.  [서평]Multimedia: Computing, Communications & Applications , 1996 .

[45]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[46]  P. Yip,et al.  CAD Methodology for the Design of UltraSPARC™ -I Microprocessor at Sun Microsystems Inc. , 1995, 32nd Design Automation Conference.

[47]  Yale N. Patt,et al.  A comparison of dynamic branch predictors that use two levels of branch history , 1993, ISCA '93.

[48]  V. Leitáo,et al.  Computer Graphics: Principles and Practice , 1995 .

[49]  Richard B. Brown Design Optimization of a GaAs RISC Microprocessor with Area-Interconnect MCM Packaging , 1999 .

[50]  Norman P. Jouppi,et al.  Computer technology and architecture: an evolving interaction , 1991, Computer.

[51]  Norman P. Jouppi,et al.  The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance , 1989, IEEE Trans. Computers.

[52]  Marc Tremblay,et al.  A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC™ -I , 1995, 32nd Design Automation Conference.

[53]  Monica S. Lam,et al.  Limits of control flow on parallelism , 1992, ISCA '92.

[54]  K. Kavi Cache Memories Cache Memories in Uniprocessors. Reading versus Writing. Improving Performance , 2022 .

[55]  Doug Matzke,et al.  Will Physical Scalability Sabotage Performance Gains? , 1997, Computer.

[56]  N. Jouppi,et al.  Tradeoffs in two-level on-chip caching , 1994, Proceedings of 21 International Symposium on Computer Architecture.

[57]  Michael Kagan,et al.  The Pentium" Processor with MMXTM Technology , 1997 .

[58]  Peter M. Kogge,et al.  The Architecture of Pipelined Computers , 1981 .

[59]  Mike Johnson,et al.  Superscalar microprocessor design , 1991, Prentice Hall series in innovative technology.

[60]  David L. Kuck,et al.  The Structure of Computers and Computations , 1978 .

[61]  Alan Jay Smith,et al.  Branch Prediction Strategies and Branch Target Buffer Design , 1995, Computer.

[62]  PA-8000 Combines Complexity and Speed: 11/14/94 , 1994 .

[63]  Burton M. Leary,et al.  A 200 MHz 64 b dual-issue CMOS microprocessor , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[64]  James C. Miller,et al.  Computer graphics principles and practice, second edition , 1992, Comput. Graph..

[65]  Steven A. Przybylski,et al.  Cache and memory hierarchy design: a performance-directed approach , 1990 .

[66]  Dirk Grunwald,et al.  Next cache line and set prediction , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.