论文信息 - A logarithmic digital-analog converter for digital CMOS technology

A logarithmic digital-analog converter for digital CMOS technology

This paper describes the design and integrated circuit implementation of a logarithmic digital-to-analogue converter employing a digitally-controlled current attenuator whose accuracy depends solely on the matching of transistors. An 8-bit resolution, 80 dB dynamic range prototype chip fabricated in a 1.2 /spl mu/m digital CMOS technology occupies 1.5 mm/sup 2/ and at 5 V supply and 1 MHz conversion rate dissipates 6 mW.

J. E. Franca | J. Guilherme | J. Guilherme | J. Franca

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