论文信息 - Extremely thin SOI (ETSOI) technology: Past, present, and future

Extremely thin SOI (ETSOI) technology: Past, present, and future

As the mainstream bulk devices face formidable challenges to scale beyond 20nm node, there is an increasingly renewed interest in fully depleted devices for continued CMOS scaling. In this paper, we provide an overview of extremely thin SOI (ETSOI), a viable fully depleted device architecture for future technology. Barriers that prevented ETSOI becoming a mainstream technology in the past are specified and solutions to overcome those barriers are provided.

[1] S. Ramey,et al. Threshold voltage calculation in ultrathin-film SOI MOSFETs using the effective potential , 2003 .

[2] T. Hiramoto,et al. Impact of SOI thickness fluctuation on threshold voltage variation in ultra-thin body SOI MOSFETs , 2005, IEEE Transactions on Nanotechnology.

[3] S. Horiguchi,et al. Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs , 1993, IEEE Electron Device Letters.

[4] G. G. Shahidi. SOI technology for the GHz era , 2002, IBM J. Res. Dev..

[5] T. Iwamatsu,et al. Smallest Vth variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate , 2008, 2008 Symposium on VLSI Technology.

[6] C. Auth,et al. 45nm High-k + metal gate strain-enhanced transistors , 2008, 2008 Symposium on VLSI Technology.

[7] W. Haensch,et al. High-Performance Undoped-Body 8-nm-Thin SOI Field-Effect Transistors , 2008, IEEE Electron Device Letters.

[8] Chenming Hu,et al. Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain , 2001 .

[9] Shinichi Takagi,et al. Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs , 2004 .

[10] Didier Landru,et al. SOI substrate readiness for 22/20 nm and for fully depleted planar device architectures , 2009, 2009 IEEE International SOI Conference.