A low-power and domain-specific reconfigurable FFT fabric for system-on-chip applications

A low-power dynamic reconfigurable FFT fabric is proposed in this paper. The architecture is served as a scalable IP core, which is suitable for system on chip applications. The system can be configured as 16, 32, 64, 128, 256, 512 and 1024-point FFT. Compared with a conventional ASIC FFT processor, this FFT fabric is characterized by having dynamic reconfigurability while incurring only a 12 /spl sim/ 19% increase in energy consumption, and requiring 14% more area than a 1024-point non-reconfigurable FFT fabric. On the other hand, compared with a FFT processor which is mapped onto a general purpose reconfigurable architecture, it has 30 /spl sim/ 94% less energy consumption.

[1]  Bevan M. Baas,et al.  A low-power, high-performance, 1024-point FFT processor , 1999, IEEE J. Solid State Circuits.

[2]  R.W. Brodersen,et al.  Architectural evaluation of flexible digital signal processing for wireless receivers , 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

[3]  Yutai Ma,et al.  An effective memory addressing scheme for FFT processors , 1999, IEEE Trans. Signal Process..

[4]  Steven J. E. Wilton,et al.  Embedded memory in FPGAs: recent research results , 1999, 1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368).

[5]  Keith Reeves,et al.  Reconfigurable hardware accelerator for embedded DSP , 1996, Other Conferences.

[6]  D. Cohen.  Simplified control of FFT hardware , 1976 .

[7]  Milos D. Ercegovac,et al.  FPGA-based structures for on-line FFT and DCT , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[8]  Jeffrey J. Cook,et al.  Clustered programmable-reconfigurable processors , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..