Timing, Logic and Mixed-Mode Simulation for Large MOS Integrated Circuits

Many different forms of simulation can be used for the analysis of large digital integrated circuit designs at the various stages of the design process. They may be classified as Behavioral (also called algorithmic or functional) simulators, Register Transfer Level (RTL) simulators, Gate Level Logic simulators, timing simulators, and circuit simulators, as illustrated in Fig.1.1.

[1]  Will Sherwood A Hybrid Scheduling Technique for Hierarchical Logic Simulators or "Close Encounters of the Simulated Kind" , 1979, 16th Design Automation Conference.

[2]  A. R. Newton,et al.  Techniques for the simulation of large-scale integrated circuits , 1979 .

[3]  H. Shichman,et al.  Modeling and simulation of insulated-gate field-effect transistor switching circuits , 1968 .

[4]  Leon O. Chua,et al.  Diakoptic and generalized hybrid analysis , 1976 .

[5]  Basant R. Chawla,et al.  Motis - an mos timing simulator , 1975 .

[6]  M.L. Liou,et al.  Computer-aided analysis of electronic circuits: Algorithms and computational techniques , 1977, Proceedings of the IEEE.

[7]  Leon O. Chua,et al.  An efficient heuristic cluster algorithm for tearing large-scale networks , 1977 .

[8]  A. Jimenez,et al.  Algorithms for ASTAP--A network-analysis program , 1973 .

[9]  Melvin A. Breuer,et al.  General survey of design automation of digital computers , 1966 .

[10]  Charles A. Desoer,et al.  Basic Circuit Theory , 1969 .

[11]  Yaohan Chu,et al.  An ALGOL-like computer design language , 1965, CACM.

[12]  Werner Liniger,et al.  Contractive methods for stiff differential equations Part II , 1978 .

[13]  A. Sangiovanni-Vincentelli,et al.  A multilevel Newton algorithm with macromodeling and latency for the analysis of large-scale nonlinear circuits in the time domain , 1979 .

[14]  Hsueh Hsieh,et al.  A latent macromodular approach to large-scale sparse networks , 1976 .

[15]  William H. Beyer Standard Mathematical Tables , 1984 .

[16]  Stephen A. Szygenda,et al.  Digital Logic Simulation in a Time-Based, Table-Driven Environment , 1975, Computer.

[17]  James M. Ortega,et al.  Iterative solution of nonlinear equations in several variables , 2014, Computer science and applied mathematics.

[18]  Stephen A. Szygenda,et al.  Modeling and Digital Simulation for Design Verification and Diagnosis , 1976, IEEE Transactions on Computers.

[19]  Leon Shalla Automatic analysis of electronic digital circuits using list processing , 1966, CACM.

[20]  Leon O. Chua,et al.  Computer-Aided Analysis Of Electronic Circuits , 1975 .

[21]  Vishwani D. Agrawal,et al.  A Mixed-Mode Simulator , 1980, 17th Design Automation Conference.

[22]  Sundaram Seshu,et al.  The Diagnosis of Asynchronous Sequential Switching Systems , 1962, IRE Trans. Electron. Comput..

[23]  Donald L. Dietmeyer,et al.  A Digital System Design Language (DDL) , 1968, IEEE Transactions on Computers.

[24]  Jesse H. Katz Optimizing bit-time computer simulation , 1963, CACM.

[25]  Donald O. Pederson,et al.  Analysis Time, Accuracy And Memory Requirement Tradeoffs In Spice2 , 1977 .

[26]  H. De Man,et al.  The Use of Threshold Functions and Boolean Controlled Network Elements for Macromodeling of ISI Circuits , 1977, ESSCIRC '77: 3rd European Solid State Circuits Conference.

[27]  James S. Jephson,et al.  A Three-Value Computer Design Verification System , 1969, IBM Syst. J..

[28]  T. I. Kirkpatrick,et al.  PERT as an aid to logic design , 1966 .