论文信息 - A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor

A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor

The feasibility of a fully integrated RF front-end using an above-IC BAW integration technique is demonstrated for WCDMA applications. The circuit has a voltage gain of 31.3dB, a noise figure of 5.3dB, an in-band IIP3 of -8dBm and IIP2 of 38dBm, with a total power consumption of 36mW. The BAW filter area is 0.45mm/sup 2/ and the total circuit area including the BAW filter is 2.44mm/sup 2/.

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