Effects of S/D non-overlap and high-/spl kappa/ dielectrics on nano CMOS design

A new MOSFET structure with non-overlap S/D to gate and high-ic spacer was proposed. Extensive simulation data and some measured data were reported. The proposed structure showed very good subthreshold slope, DIBL, GIDL compared to those of overlap structure. By controlling the non-overlap length, we could obtain reasonable speed and on-current characteristics. Also we have shown the GIDL depends on strongly the difference of the gate and the spacer dielectric constants. Based on the results, we conclude reasonable non-overlap length is between 0 (just meet the gate edge) to 10 mn.