Performance constraints for onchip optical interconnects

This work aims at defining the marks that optoelectronic solutions will have to beat for replacing electric interconnects at chip level. We first simulate the electric response of future electrical interconnects considering the reduction of the CMOS feature size /spl lambda/ from 0.7 to 0.05 /spl mu/m. We also consider the architectural evolution of chips to analyze the latency issues. We conclude that: 1) it does not seem necessary in the future chips to consider the integration of optical interconnects (OIs) over distances shorter than 1000-2000 /spl lambda/, because the performance of electric interconnects is sufficient; 2) the penetration of OIs over distances longer than 10/sup 4//spl lambda/ could be envisaged (on the sole basis of the performance limitation) provided that it will be possible to demonstrate new generations of (cheap and CMOS-compatible) low-threshold high-efficiency vertical cavity surface emitting lasers (VCSELs) and ultrafast high-efficiency photodiodes; 3) the first possible application of onchip OIs is likely not for interblock communication but for clock distribution as the energy constraints (imposed by the evolution of CMOS technology) are weaker and because the clock tree is an extremely long interconnect.

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