Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP

A parallel signal processor architecture has been developed for real time motion picture encoding. The architecture is based on spatial parallelism utilization in a picture signal. Plural element processors handle subregional pictures simultaneously without communicating with other element processors. However, due to an overlapsave technique where every sub-picture input area is chosen to be wider than the output area, element processors can carry out continuous processing over an entire picture. In order to increase motion picture processing efficiency as well as system implementation simplicity, a specific element processor LSI chip, composed of a pipeline arithmetic unit, two dimensional address generators, a raster scan signal handler, and a sequence controller, has been developed by using more than 220,000 transistors. The developed parallel processor is shown to be applicable to a software programmable low bit rate TV codec.