2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC
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Gordon Gammie | Rolf Lagerquist | Ashish Nayak | Manzur Rahman | Vincent Lin | Ericbill Wang | Achuta Thippana | Hugh Mair | Loda Chou | Hsinchen Chen | Lee-Kee Yong | Jenny Wiedemeier | Ramu Madhavaram | Alex Chiou | Blundt Li | Rory Huang | Michael Yanq | Osric Su | SA Huang | H. Mair | V. Lin | G. Gammie | Ramu Madhavaram | Ashish Nayak | HsinChen Chen | R. Lagerquist | Jenny Wiedemeier | A. Thippana | Ericbill Wang | Rory Huang | Alex Chiou | Loda Chou | Lee-Kee Yong | Manzur Rahman | Blundt Li | Michael Yanq | Osric Su | S. A. Huang
[1] Samuel Naffziger,et al. 5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[2] Uming Ko,et al. 3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).
[3] Keith A. Bowman,et al. A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance , 2013, IEEE Journal of Solid-State Circuits.