Frequency-Domain-Multiplexing Single-Wire Interface and Harmonic-Rejection-Based IF Data De-Multiplexing in Millimeter-Wave MIMO Arrays

Recently, mm-wave multi-in multi-out (MIMO) arrays are garnering significant attention because of their ability to form multiple spatial beams, achieving significantly higher data rates compared to traditional phased array-based approaches. Furthermore, scalable MIMO arrays can provide many other functionalities, such as full digital beamforming and per-power amplifier (PA) digital pre-distortion. In this work, an MIMO four-element TX array architecture is presented with a frequency-domain multiplexing-based single-wire interface (SWI), breaking the tradeoff between channel-to-channel isolation and single wire (SW) bandwidth (BW). The concept of harmonic-rejection mixing (HRM) is used to de-multiplex the four modulated signals simultaneously from the SW using a single passive mixer driven by a multi-phase local oscillator (LO). The two-stage harmonic recombination circuits are implemented in baseband and, hence, achieve high channel-to-channel isolation with a low power overhead. A 60-GHz four-element TX prototype demonstrates the proposed architecture in 45-nm RF silicon-on-insulator (RFSOI) CMOS. The frequency-division-multiplexed (FDM)-based SWI can support 8-GHz total intermediate frequency (IF) BW across the four channels with 30–40-dB channel-to-channel isolation. Each TX element in the array achieves 20–35-dB conversion gain and +8.8–10.9-dBm OP1dB while consuming 225 mW/element.

[1]  Chun-Geik Tan,et al.  A Multiband Mobile Analog TV Tuner SoC With 78-dB Harmonic Rejection and GSM Blocker Detection in 65-nm CMOS , 2013, IEEE Journal of Solid-State Circuits.

[2]  Shuhei Yamada,et al.  A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS , 2018, IEEE Journal of Solid-State Circuits.

[3]  David Murphy,et al.  A 60-GHz 144-Element Phased-Array Transceiver for Backhaul Application , 2018, IEEE Journal of Solid-State Circuits.

[4]  Jri Lee,et al.  Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies , 2015, IEEE Journal of Solid-State Circuits.

[5]  Eric A. M. Klumperink,et al.  A digital sine-weighted switched-Gm mixer for single-clock power-scalable parallel receivers , 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

[6]  Shahriar Shahramian,et al.  A Fully Integrated 384-Element, 16-Tile, $W$ -Band Phased Array With Self-Alignment and Self-Test , 2019, IEEE Journal of Solid-State Circuits.

[7]  Harish Krishnaswamy,et al.  Arbitrary Analog/RF Spatial Filtering for Digital MIMO Receiver Arrays , 2017, IEEE Journal of Solid-State Circuits.

[8]  Kristofer S. J. Pister,et al.  An ultra-low power 900 MHz RF transceiver for wireless sensor networks , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[9]  Hongtao Zhang,et al.  A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET , 2019, IEEE Journal of Solid-State Circuits.

[10]  Ranjit Gharpurey,et al.  Design and Analysis of Harmonic Rejection Mixers With Programmable LO Frequency , 2013, IEEE Journal of Solid-State Circuits.

[11]  Min-Yu Huang,et al.  A Mm-Wave Wideband MIMO RX With Instinctual Array-Based Blocker/Signal Management for Ultralow-Latency Communication , 2019, IEEE Journal of Solid-State Circuits.

[12]  Arun Natarajan,et al.  A Scalable 60GHz 4-Element MIMO Transmitter with a Frequency-Domain-Multiplexing Single-Wire Interface and Harmonic-Rejection-Based De-Multiplexing , 2020, 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

[13]  Li Lin,et al.  A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[14]  Shuhei Yamada,et al.  A 42.2-Gb/s 4.3-pJ/b 60-GHz Digital Transmitter With 12-b/Symbol Polarization MIMO , 2019, IEEE Journal of Solid-State Circuits.

[15]  Gabriel M. Rebeiz,et al.  A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a $2\times 2$ Beamformer Flip-Chip Unit Cell , 2018, IEEE Journal of Solid-State Circuits.

[16]  Lei Zhou,et al.  A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET , 2017, IEEE Journal of Solid-State Circuits.

[17]  Harish Krishnaswamy,et al.  Scalable Spatial Notch Suppression in Spatio-Spectral-Filtering MIMO Receiver Arrays for Digital Beamforming , 2016, IEEE Journal of Solid-State Circuits.

[18]  Harish Krishnaswamy,et al.  A 4-channel 4-beam 24-to-26GHz spatio-temporal RAKE radar transceiver in 90nm CMOS for vehicular radar applications , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[19]  Maryam Rofougaran,et al.  A 16TX/16RX 60 GHz 802.11ad Chipset With Single Coaxial Interface and Polarization Diversity , 2014, IEEE Journal of Solid-State Circuits.

[20]  Hiroyuki Kobayashi,et al.  30.3 A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

[21]  Harish Krishnaswamy,et al.  High-Power High-Efficiency Class-E-Like Stacked mmWave PAs in SOI and Bulk CMOS: Theory and Implementation , 2014, IEEE Transactions on Microwave Theory and Techniques.

[22]  Peter J. Vancorenland,et al.  A harmonic rejection mixer robust to RF device mismatches , 2011, 2011 IEEE International Solid-State Circuits Conference.

[23]  Ranjit Gharpurey,et al.  A 2 GS/s Frequency-Folded ADC-Based Broadband Sampling Receiver , 2014, IEEE Journal of Solid-State Circuits.

[24]  Kenichi Okada,et al.  A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio , 2019, IEEE Journal of Solid-State Circuits.

[25]  Eric A. M. Klumperink,et al.  A software-defined radio receiver architecture robust to out-of-band interference , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[26]  Duixian Liu,et al.  A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications , 2017, IEEE Journal of Solid-State Circuits.

[27]  Peter M. Asbeck,et al.  Analysis and Design of Stacked-FET Millimeter-Wave Power Amplifiers , 2013, IEEE Transactions on Microwave Theory and Techniques.

[28]  Harish Krishnaswamy,et al.  Analysis and Design of a Full-Duplex Two-Element MIMO Circulator-Receiver With High TX Power Handling Exploiting MIMO RF and Shared-Delay Baseband Self-Interference Cancellation , 2019, IEEE Journal of Solid-State Circuits.

[29]  Harish Krishnaswamy,et al.  Code-Domain Multiplexing for Shared IF/LO Interfaces in Millimeter-Wave MIMO Arrays , 2020, IEEE Journal of Solid-State Circuits.

[30]  Sanket Jain,et al.  A 10GHz CMOS RX frontend with spatial cancellation of co-channel interferers for MIMO/digital beamforming arrays , 2016, 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).