Multithreading decoupled architectures for complexity-effective general purpose computing
暂无分享,去创建一个
[1] James E. Smith,et al. Complexity-Effective Superscalar Processors , 1997, ISCA.
[2] Stamatis Vassiliadis,et al. On the design complexity of the issue logic of superscalar machines , 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).
[3] E SmithJames. Dynamic Instruction Scheduling and the Astronautics ZS-1 , 1989 .
[4] Alasdair Rawsthorne,et al. Compiling and optimizing for decoupled architectures , 1995 .
[5] Nigel P. Topham,et al. Performance of the decoupled ACRI-1 architecture: the perfect club , 1995, HPCN Europe.
[6] Andrew R. Pleszkun,et al. PIPE: a VLSI decoupled architecture , 1985, ISCA '85.
[7] Gary S. Tyson,et al. MISC: a Multiple Instruction Stream Computer , 1992, MICRO 1992.
[8] Antonio González,et al. The synergy of multithreading and access/execute decoupling , 1999, Proceedings Fifth International Symposium on High-Performance Computer Architecture.
[9] Richard E. Kessler,et al. The Alpha 21264 microprocessor , 1999, IEEE Micro.
[10] Vojin G. Oklobdzija,et al. Multithreaded Decoupled Architecture , 1995, Int. J. High Speed Comput..
[11] Vikas Agarwal,et al. Clock rate versus IPC: the end of the road for conventional microarchitectures , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).
[12] Pius Ng,et al. A comparision of superscalar and decoupled access/execute architectures , 1993, MICRO 1993.
[13] Antonio González,et al. Speculative multithreaded processors , 1998, ICS '98.
[14] Vivek Sarkar,et al. Baring It All to Software: Raw Machines , 1997, Computer.
[15] Theo Ungerer,et al. Context-switching techniques for decoupled multithreaded processors , 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.
[16] Alasdair Rawsthorne,et al. Compiling and Optimizing for Decoupled Architectures , 1995, Proceedings of the IEEE/ACM SC95 Conference.
[17] Alasdair Rawsthorne,et al. The effectiveness of decoupling , 1993, ICS '93.
[18] Joan-Manuel Parcerisa,et al. Multithreaded Decoupled Access/Execute Processors , 1997 .
[19] Wm. A. Wulf. Evaluation of the WM architecture , 1992, ISCA '92.
[20] J.E. Smith,et al. The Astronautics ZS-1 processor , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.
[21] Josep Llosa,et al. The Performance of Decoupled Architectures1 , 1996 .
[22] Andrew R. Pleszkun,et al. PIPE: a VLSI decoupled architecture , 1985, ISCA '85.
[23] Josep Llosa,et al. Performance Diagnostics of the ACRI-1 , 1996 .
[24] Nigel P. Topham,et al. A comparison of data prefetching on an access decoupled and superscalar machine , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.