Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications
暂无分享,去创建一个
Patrick Girard | Xiaoqing Wen | Yan Chen | Zhili Chen | Jie Cui | Aibin Yan | Zhelong Xu | Zhengfeng Huang | P. Girard | X. Wen | Zhengfeng Huang | Aibin Yan | Zhili Chen | Zhelong Xu | Jie Cui | Yan Chen
[1] T. Calin,et al. Upset hardened memory design for submicron CMOS technology , 1996 .
[2] Kiamal Z. Pekmestzi,et al. DONUT: A Double Node Upset Tolerant Latch , 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.
[3] Maryam Shojaei Baghini,et al. Robust Soft Error Tolerant CMOS Latch Configurations , 2016, IEEE Transactions on Computers.
[4] Yiorgos Tsiatouhas,et al. Soft error interception latch: double node charge sharing SEU tolerant design , 2015 .
[5] Spyros Tragoudas,et al. Radiation Hardened Latch Designs for Double and Triple Node Upsets , 2017, IEEE Transactions on Emerging Topics in Computing.
[6] Wenjuan Lu,et al. Read/write margin enhanced 10T SRAM for low voltage application , 2016, IEICE Electron. Express.
[7] Xiaoqing Wen,et al. Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[8] J. S. Kauppila,et al. An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology , 2016, IEEE Transactions on Nuclear Science.
[9] Kang Yang,et al. Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS , 2018, 2018 IEEE 27th Asian Test Symposium (ATS).
[10] Yong-Bin Kim,et al. A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories , 2016, IEEE Transactions on Computers.
[11] Tianqi Wang,et al. Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology , 2015, Microelectron. Reliab..
[12] Kiamal Z. Pekmestzi,et al. DIRT latch: A novel low cost double node upset tolerant latch , 2017, Microelectron. Reliab..
[13] Huaguo Liang,et al. A High Performance SEU Tolerant Latch , 2015, J. Electron. Test..
[14] Jaspal Singh Shah,et al. A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS , 2015, IEEE Transactions on Nuclear Science.
[15] Yuanqing Li,et al. Double Node Upsets Hardened Latch Circuits , 2015, J. Electron. Test..
[16] Qiang Zhao,et al. Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[17] Ahmad Patooghy,et al. Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies , 2009, IET Comput. Digit. Tech..
[18] P. E. Dodd,et al. Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction , 2013, IEEE Transactions on Nuclear Science.
[19] Xu Hui,et al. Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches , 2015, IEICE Electron. Express.
[20] Kohei Miyase,et al. Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments , 2020, IEEE Transactions on Aerospace and Electronic Systems.
[21] Ziyang Chen,et al. A radiation harden enhanced Quatro (RHEQ) SRAM cell , 2017, IEICE Electron. Express.
[22] Vojin G. Oklobdzija,et al. Low-Power Soft Error Hardened Latch , 2009, PATMOS.
[23] Cecilia Metra,et al. High-Performance Robust Latches , 2010, IEEE Transactions on Computers.
[24] M. Gadlage,et al. Soft Errors Induced by High-Energy Electrons , 2017, IEEE Transactions on Device and Materials Reliability.
[25] Mahdi Fazeli,et al. Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation , 2013, Microelectron. Reliab..
[26] T.M. Mak,et al. Built-In Soft Error Resilience for Robust System Design , 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.
[27] Fei Yu,et al. Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits , 2019, J. Electron. Test..
[28] Bahar Asgari,et al. Design of Robust SRAM Cells Against Single-Event Multiple Effects for Nanometer Technologies , 2015, IEEE Transactions on Device and Materials Reliability.
[29] Xiaoqing Wen,et al. Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS , 2018, IEEE Transactions on Emerging Topics in Computing.