Test structure, circuits and extraction methods to determine the radius of infuence of STI and polysilicon pattern density
暂无分享,去创建一个
Advanced CMOS processes need new methodologies to extract, characterize and model process variations and their sources. Most prior studies have focused on understanding the effect of local layout features on transistor performance; limited work has been done to characterize medium-range (≈ 10μm to 2mm) pattern density effects. We propose a new methodology to extract the radius of influence, or the range of neighboring layout that should be taken into account in determining transistor characteristics, for shallow trench isolation (STI) and polysilicon pattern density. A test chip, with 130k devices under test (DUTs) and step-like pattern density layout changes, is designed in 65nm bulk CMOS technology as a case study. The extraction result of the measured data suggests that the local layout geometry, within the DUT cell size of 6μm × 8μm, is the dominant contributor to systematic device variation. Across-die medium-range layout pattern densities are found to have a statistically significant and detectable effect, but this effect is small and contributes only 2-5% of the total variation in this technology.
[1] Y. Sonobe,et al. Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics , 2004, IEEE Transactions on Electron Devices.
[2] Osama M. Nayfeh,et al. Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations , 2006, IBM J. Res. Dev..