Power6 Decimal Divide

The IEEE 754-R floating-point standard has defined the arithmetic and encodings of the new decimal floating-point format. The C and C++ standards as well as other language standards have proposed a new data type to help programmers exploit the performance of this new hardware format. The IBM Power6 microprocessor will soon release the first hardware implementation of this decimal floating-point format. A discussion of how the decimal division operation is implemented in high frequency BCD hardware and a comparison to other division methods is provided. This implementation reuses some popular binary division algorithms such as prescaling and non-restoring division to reduce the amount of additional hardware. Novel twists are applied to these algorithms to adapt them for BCD formatted numbers.

[1]  F.Y. Busaba,et al.  The IBM z900 decimal arithmetic unit , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[2]  Michael J. Schulte,et al.  Decimal floating-point division using Newton-Raphson iteration , 2004, Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004..

[3]  Tomás Lang,et al.  On-the-Fly Conversion of Redundant into Conventional Representations , 1987, IEEE Transactions on Computers.

[4]  Jan Fandrianto.  Algorithm for high speed shared radix 8 division and radix 8 square root , 1989, Proceedings of 9th Symposium on Computer Arithmetic.

[5]  M. Ercegovac,et al.  Division and Square Root: Digit-Recurrence Algorithms and Implementations , 1994 .

[6]  E. V. Krishnamurthy,et al.  On Range-Transformation Techniques for Division , 1970, IEEE Transactions on Computers.

[7]  Robert E Goldschmidt,et al.  Applications of division by convergence , 1964 .

[8]  S. F. Anderson,et al.  The IBM system/360 model 91: floating-point execution unit , 1967 .

[9]  M.A. Erle,et al.  Potential speedup using decimal floating-point hardware , 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..

[10]  Jan Fandrianto.  Algorithm for high speed shared radix 4 division and radix 4 square-root , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[11]  Mark Horowitz,et al.  SRT division architectures and implementations , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.

[12]  Tomás Lang,et al.  Simple Radix-4 Division with Opterands Scaling , 1990, IEEE Trans. Computers.

[13]  R. K. Richards,et al.  Arithmetic operations in digital computers , 2013 .