VHDL based design parameterization methodology

With the fast development of FPGA manufacture technology,more and more algorithms can be implemented on FPGA.Although VHDL has its own portability,a design’s portability acquires the management of scale with specify FPGA chip.Besides one kind of algorithm can be applied to many areast,he size of design should be adaptive to particular application.Design parameterization is a design method that can generate designs of various processing capability by corresponded parameters.Design parameterization is an efficient way for portability.This paper firstly proposes a synthesis tool based param-eterization method on VHDL,secondly illustrates detail operations with design of a multi-way parity checksum generator,and finally applies the parameterization technique onto a FPGA implementation of HMMer.The parameterization method proposed by this paper has simple operations,minimal code change,and no dependency to executable code generators.Experiment shows that it is a low cost but highly efficient parameterization solution.