A method of segmenting digital-to-analog converters

Segmented architectures are often used in digital-to-analog converters (DACs). Here we propose a DAC structure based on recursive decomposition of an N-bit binary DAC into two (N-1) bit DACs and one 1 bit DAC. A DAC model that includes matching errors has been simulated. The simulation results indicate that by using four layers of decomposition it is possible to achieve similar performance as when using seven bits of traditional segmentation.