121.15MHz Frequency Synthesizers using Multi-phase DLL-based Phase Selector and Fractional-N PLL

ABSTRACT Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 mm 2 and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 mm 2 and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW. 키워드 : 주파수 합성기, 다중위상 지연고정루프, 위상 선택기, 분수 분주형 위상고정루프 Key word :