FPGA implementation of a video-rate fluorescence lifetime imaging system with a 32×32 CMOS single-photon avalanche diode array

A new integration based fluorescence lifetime imaging microscopy (FLIM) called IEM has been proposed to implement lifetime calculations [1]. A real-time hardware implementation of this IEM FLIM algorithm suitable for a single photon avalanche diode (SPAD) array in 0.13µm CMOS technology is now implemented on FPGA. A widefield microscope was adapted to accommodate the array and test it on biological applications. Video-rate fluorescence lifetime imaging has been achieved, by performing parallel 32×32 lifetime calculations, realizing the first, compact, and low-cost FLIM camera.

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