Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures

In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. These are targeted for ultra low power consumption applications. The elementary gates used are threshold logic gates (perceptrons). Simulations have been performed both with and without considering the delay on the wires. These simulations confirm that wires play a significant role, reducing the speed advantage of the parallel adder (over the serial one) from 4.5x to 2.2–2.4x. A promising result is that the speed of both adders improves more than 10x when migrating from 100nm to 70nm. The full adder based on threshold logic gates (used in the ripple carry adder) improves on previously known full adders, achieving 1.6fJ when operated at 200mV in 120nm CMOS. Finally, the speed of the parallel adder can be matched by the serial adder when operating at only 10–20% higher Vdd, while still requiring less power and energy.

[1]  Derek Abbott,et al.  Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/threshold-logic approach , 2004, IEEE Computer Society Annual Symposium on VLSI.

[2]  P. Gargini,et al.  The International Technology Roadmap for Semiconductors (ITRS): "Past, present and future" , 2000, GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuits Symposium. 22nd Annual Technical Digest 2000. (Cat. No.00CH37084).

[3]  Alan F. Murray,et al.  IEEE International Conference on Neural Networks , 1997 .

[4]  Nathan Ickes,et al.  Design considerations for next generation wireless power-aware microsensor nodes , 2004, 17th International Conference on VLSI Design. Proceedings..

[5]  Valeriu Beiu,et al.  VLSI implementations of threshold logic-a comprehensive survey , 2003, IEEE Trans. Neural Networks.

[6]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[7]  Tor Sverre Lande,et al.  FLOGIC-Floating-gate logic for low-power operation , 1996, Proceedings of Third International Conference on Electronics, Circuits, and Systems.

[8]  Valeriu Beiu.  A novel highly reliable low-power nano architecture when von Neumann augments Kolmogorov , 2004 .

[9]  Y. Arima,et al.  A 9/spl mu/W 50MHz 32b adder using a self-adjusted forward body bias in SoCs , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[10]  U. Ruckert,et al.  On nanoelectronic architectural challenges and solutions , 2004, 4th IEEE Conference on Nanotechnology, 2004..

[11]  Kaushik Roy,et al.  Robust subthreshold logic for ultra-low power operation , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Valeriu Beiu,et al.  Constructive Threshold Logic Addition A Synopsis of the Last Decade , 2003, ICANN.

[13]  Kaushik Roy,et al.  Ultra-low power DLMS adaptive filter for hearing aid applications , 2001, ISLPED '01.

[14]  B.C. Paul,et al.  Device optimization for digital subthreshold logic operation , 2005, IEEE Transactions on Electron Devices.

[15]  Yu Cao,et al.  New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[16]  J. Shott,et al.  A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[17]  Valeriu Beiu,et al.  Characterization of a 16-bit threshold logic single-electron technology adder , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[18]  Erkki Oja,et al.  Artificial Neural Networks and Neural Information Processing — ICANN/ICONIP 2003 , 2003, Lecture Notes in Computer Science.

[19]  Snorre Aunet,et al.  Four-MOSFET Floating-Gate UV-Programmable Elements for Multifunction Binary Logic , 2001 .

[20]  Yoshihito Amemiya,et al.  Single-Electron Majority Logic Circuits , 1997 .

[21]  Y. Berg,et al.  Reconfigurable subthreshold CMOS perceptron , 2004, 2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541).

[22]  Benton H. Calhoun,et al.  Device sizing for minimum energy operation in subthreshold circuits , 2004 .