Symbolic Time-Varying Root-Locus Analysis for

[1]  William H. Press,et al.  Numerical Recipes in C, 2nd Edition , 1992 .

[2]  Guoyong Shi,et al.  A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits , 2011, Analog Integrated Circuits and Signal Processing.

[3]  C.-J. Richard Shi,et al.  A Graph Reduction Approach to Symbolic Circuit Analysis , 2007, 2007 Asia and South Pacific Design Automation Conference.

[4]  L. Zadeh,et al.  Frequency Analysis of Variable Networks , 1950, Proceedings of the IRE.

[5]  S. Haley,et al.  The generalized eigenproblem: pole-zero computation , 1988, Proceedings of the IEEE.

[6]  Y. Tsividis Operation and modeling of the MOS transistor , 1987 .

[7]  Jacob K. White,et al.  Fundamentals of Fast Simulation Algorithms for RF Circuits , 2007, Proceedings of the IEEE.

[8]  Kartikeya Mayaram,et al.  Computer-aided circuit analysis tools for RFIC simulation: algorithms, features, and limitations , 2000 .

[9]  Sheldon X.-D. Tan,et al.  Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Sheldon X.-D. Tan,et al.  Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  Svetozar S. Broussev,et al.  Time-Varying Root-Locus of Large-Signal LC Oscillators , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.