System modeling and multicore simulation using transactions

With the increasing complexity of digital systems that are becoming more and more parallel, a better abstraction to describe such systems has become a necessity. This paper shows how, by using the powerful mechanism of transactions as a concurrency model, and by taking advantage of .NET introspection and attribute programming capabilities, we were able to develop a system-level modeling and parallel simulation environment. We kept the same concepts to describe the architecture of high-level models, such as modules and communication channels. However, unlike SystemC, the behaviour is no longer described as processes and events but as transactions. We implemented scheduling algorithms in order to enable simulating a transactional models in parallel by taking advantage of a multicore machine. These algorithms take into account the dependency between transactions and the number of cores of the simulation machine. We studied two synchronisation strategies: one using locking and the other using partitioning. An experiment made on a WiFi 802.11a transmitter achieved a speedup of about 1.9 using two threads. With 8 threads, although the workload of individual transactions was not significant, we could reach a 5.1 speedup. When the workload is significant the speedup can reach 6.3.

[1]  Stephan Merz,et al.  Verifying Safety Properties with the TLA+ Proof System , 2010, IJCAR.

[2]  C. Bron,et al.  Algorithm 457: finding all cliques of an undirected graph , 1973 .

[3]  René van Leuken,et al.  Extracting behavior and dynamically generated hierarchy from SystemC models , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[4]  Simon L. Peyton Jones,et al.  Composable memory transactions , 2005, CACM.

[5]  Q. W. Xu On Compositionality in Refining Concurrent Systems , 1996 .

[6]  Leslie Lamport,et al.  Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers [Book Review] , 2002, Computer.

[7]  Kevin Marquet,et al.  PinaVM: a systemC front-end based on an executable intermediate representation , 2010, EMSOFT '10.

[8]  Leslie Lamport,et al.  The temporal logic of actions , 1994, TOPL.

[9]  Erich Prisner Clique Covering and Clique Partition in Generalizations of Line Graphs , 1995, Discret. Appl. Math..

[10]  Gottfried Vossen,et al.  Transactional Information Systems: Theory, Algorithms, and the Practice of Concurrency Control and Recovery , 2002 .

[11]  Mike Barnett,et al.  Annotations for (more) Precise Points-to Analysis , 2007 .

[12]  El Mostapha Aboulhamid,et al.  Introspection mechanisms for runtime verification in a system-level design environment , 2009, Microelectron. J..

[13]  Matteo Fischetti Clique tree inequalities define facets of the asymmetric traveling salesman polytope , 1995 .

[14]  Andreas Gerstlauer,et al.  Multi-core parallel simulation of System-level Description Languages , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[15]  Sandeep K. Shukla,et al.  Tackling an Abstraction Gap: Co-simulating SystemC DE with Bluespec ESL , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[16]  Arvind,et al.  802.11a transmitter: a case study in microarchitectural exploration , 2006, Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings..

[17]  James R. Larus,et al.  Transactional memory , 2008, CACM.

[18]  Franco Fummi,et al.  A Smooth Refinement Flow for Co-designing HW and SW Threads , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[19]  Qiwen Xu On Compositionality in Refining Concurrent Systems , 1996 .

[20]  Paolo Toth,et al.  Models and heuristic algorithms for a weighted vertex coloring problem , 2009, J. Heuristics.

[21]  Sandeep K. Shukla,et al.  Efficient Usage of Concurrency Models in an Object-Oriented Co-design Framework , 2001 .

[22]  Martín Abadi,et al.  Conjoining specifications , 1995, TOPL.

[23]  Kevin Marquet,et al.  A Theoretical and Experimental Review of SystemC Front-ends , 2010, FDL.

[24]  Alain Greiner,et al.  Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[25]  Maged M. Michael,et al.  Software Transactional Memory: Why Is It Only a Research Toy? , 2008, ACM Queue.

[26]  Edsger W. Dijkstra,et al.  A Discipline of Programming , 1976 .

[27]  Moshe Y. Vardi Formal Techniques for SystemC Verification; Position Paper , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[28]  Sandeep K. Shukla,et al.  Concurrency in System Level Design: Conflict Between Simulation and Synthesis Goals , 2002, IWLS.

[29]  Vijay V. Vazirani,et al.  Approximation Algorithms , 2001, Springer Berlin Heidelberg.

[30]  Gabriela Nicolescu,et al.  A new efficient EDA tool design methodology , 2006, TECS.

[31]  Yvon Savaria,et al.  Modeling and simulation of complex heterogeneous systems , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[32]  Jayadev Misra A Logic for Concurrent Programming: Safety , 2003 .

[33]  James R. Larus,et al.  Transactional Memory, 2nd edition , 2010, Transactional Memory.

[34]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .

[35]  Yvon Savaria,et al.  Using Transaction-Based Models for System Design and Simulation , 2009 .