POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent
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Ansuman Banerjee | Subhankar Mukherjee | Pallab Dasgupta | Kevin Harer | Ajit Pal | Rajdeep Mukherjee | Aritra Hazra
[1] Michael Gschwind,et al. New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors , 2003, IBM J. Res. Dev..
[2] Witold A. Pleskacz,et al. Enhanced LEON3 Low Power IP Core for DSM technologies , 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.
[3] Pallab Dasgupta,et al. Formal Verification of Architectural Power Intent , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[4] Amit Srivastava,et al. Low Power Verification Methodology Using UPF Freddy , 2009 .
[5] Anantha P. Chandrakasan,et al. Low Power Digital CMOS Design , 1995 .
[6] Shireesh Verma. A Special Issue on Low Power Design and Verification Techniques , 2011, J. Low Power Electron..
[7] Kaushik Roy,et al. Low-Power CMOS VLSI Circuit Design , 2000 .
[8] Witold A. Pleskacz,et al. Enhanced LEON3 core for superscalar processing , 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.
[9] Pradip Bose,et al. Multicore power management: Ensuring robustness via early-stage formal verification , 2009, 2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design.
[10] Daniel Kroening,et al. SATABS: SAT-Based Predicate Abstraction for ANSI-C , 2005, TACAS.
[11] Stephan Merz,et al. Model Checking , 2000 .
[12] Margaret Martonosi,et al. An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).
[13] Subhankar Mukherjee,et al. Formal Verification of Hardware / Software Power Management Strategies , 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.
[14] Wolfgang Ecker,et al. Model reduction techniques for the formal verification of hardware dependent software , 2010, 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT).
[15] Jiing-Yuan Lin,et al. Experiences of low power design implementation and verification , 2008, 2008 Asia and South Pacific Design Automation Conference.
[16] Pallab Dasgupta,et al. Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent , 2010, Design Automation Conference.
[17] Allan Crone,et al. Functional Verification of Low Power Designs at RTL , 2007, PATMOS.
[18] Mohamed I. Elmasry,et al. Low Power Digital Vlsi Design , 2015 .
[19] Ansuman Banerjee,et al. Formal methods for coverage analysis of architectural power states in power-managed designs , 2012, 17th Asia and South Pacific Design Automation Conference.