RSA Power Analysis Obfuscation: A Dynamic Algorithmic Hardware Countermeasure

The modular exponentiation operation used in popular public key encryption schemes, such as RSA, has been the focus of many side channel analysis (SCA) attacks in recent years. Current SCA attack countermeasures are static, referring to the algorithmic elements as implemented in hardware. Given sufficient signal-to-noise ratio and a number of power traces, static countermeasures can be defeated, as they merely attempt to hide the power consumption of the system under attack. This paper develops a dynamic countermeasure which constantly varies the timing and power consumption of each operation, making correlation between traces more difficult. By randomizing the radix of encoding for Booth multiplication and randomizing the window size for exponentiation, we demonstrate a SCA countermeasure can be constructed which increases RSA SCA attack protection up to at least 100,000 encryption cycles, as well as a reduced execution time due to a reduction in required operations.

[1]  Adi Shamir,et al.  A method for obtaining digital signatures and public-key cryptosystems , 1978, CACM.

[2]  Sedat Soydan Analyzing the DPA Leakage of the Masked S-box via Digital Simulation and Reducing the Leakage by Inserting Delay Cells , 2010, 2010 Fourth International Conference on Emerging Security Information, Systems and Technologies.

[3]  Alfred Menezes,et al.  Handbook of Applied Cryptography , 2018 .

[4]  Sylvain Guilley,et al.  Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[5]  Aaas News,et al.  Book Reviews , 1893, Buffalo Medical and Surgical Journal.

[6]  Hsie-Chia Chang,et al.  A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Andrew D. Booth,et al.  A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[8]  Stefan Mangard,et al.  Implementation aspects of the DPA-resistant logic style MDPL , 2006, 2006 IEEE International Symposium on Circuits and Systems.