Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models
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To achieve delay balance, instead of making the faster path slower by enlongating bmnches, we make slower paths faster by sizing. Given a general clock network, which may includes loops, together with a set of feasible widths for each branch, we formulate the optimal sizing of the clock network as a constrained Optimization problem. B y turning the skew minimization problem into a least-squares estimation problem, a modified Gauss-Marquardt’s method is used to determine the optimal widths. A n ef ic ient initial sizing algorithm is proposed to speed up the sizing process. Instead of using zero-order delay model (path length) or one-order delay model (Elmore delay), we employ a generalized delay model which can handle general RLC and transmission line networks. Experimental results show that this method significantly reduces both the clock skew and path delays from source to terminals.
[1] Yung-Tao Lin,et al. Properties of interconnection on silicon, sapphire, and semi-insulating gallium arsenide substrates , 1982, IEEE Transactions on Electron Devices.