A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros

Spike sorting processors with high energy efficiency are widely used in large-scale neural signal processing tasks to monitor the activity of neurons in brains. This paper presents a low-power processor for high-accuracy spike sorting and on-chip incremental learning using an algorithm-hardware co-design approach. The processor introduces an event-driven mechanism with adaptive-threshold detection to conditionally activate the system in order to reduce power consumption. Sparsity-aware computing-in-memory (CIM) macros are also developed in our design to store templates and perform complicated computations efficiently. The prototype is designed using 28nm technology with an area of 0.018 mm2/channel and an overall power efficiency of $\mathbf{2.53} \mu \mathbf{W}/\mathbf{channel}$ and 84nW/(channel.cluster) at the voltage of 0.72V. Moreover, the accuracy of the whole design can reach 94.5% in a 32-channel scenario.

[1]  G. Cauwenberghs,et al.  A Neuromorphic Brain Interface Based on RRAM Crossbar Arrays for High Throughput Real-Time Spike Sorting , 2022, IEEE Transactions on Electron Devices.

[2]  Meilin Liu,et al.  COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning , 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

[3]  Dongsuk Jeon,et al.  A Multi-Channel Spike Sorting Processor With Accurate Clustering Algorithm Using Convolutional Autoencoder , 2021, IEEE Transactions on Biomedical Circuits and Systems.

[4]  A. Richardson,et al.  A 10.8 µW Neural Signal Recorder and Processor With Unsupervised Analog Classifier for Spike Sorting , 2021, IEEE Transactions on Biomedical Circuits and Systems.

[5]  Ryad Benosman,et al.  A Mixed-Signal Spatio-Temporal Signal Classifier for On-Sensor Spike Sorting , 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

[6]  Liangjian Lyu,et al.  A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission , 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Yan Han,et al.  Unsupervised and real-time spike sorting chip for neural signal processing in hippocampal prosthesis , 2019, Journal of Neuroscience Methods.

[8]  Pierre Yger,et al.  A spike sorting toolbox for up to thousands of electrodes validated with ground truth recordings in vitro and in vivo , 2018, eLife.

[9]  Zoltán Kincses,et al.  FPGA-based neural probe positioning to improve spike sorting with OSort algorithm , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[10]  Matteo Carandini,et al.  Kilosort: realtime spike-sorting for extracellular electrophysiology with hundreds of channels , 2016, bioRxiv.

[11]  Vaibhav Karkare,et al.  A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering , 2011, IEEE Journal of Solid-State Circuits.

[12]  Dennis Sylvester,et al.  An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With $0.175~\mu$ W/Channel in 65-nm CMOS , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  B. Upadhyaya.  Sorting , 2019, Data Structures and Algorithms with Scala.