Low-Power SDR Design on an FPGA for Intersatellite Communications

Small satellite systems make space missions for communication, navigation, and scientific research more realizable and diversified. Small satellites flying in large cluster or constellation formation as a network can provide an economical access to accomplish more complex missions, such as distributed computation, high-resolution imaging, and spacecraft maintenance. An increasing number of satellites operating on lower earth orbit for complex missions require a wireless communication system that is both reliable and flexible. This paper presents a complete software-defined radio (SDR) model for intersatellite communications (ISCs) and its implementation on a field-programmable gate array (FPGA). The proposed SDR for transmitter and receiver only has a power consumption of 2.1 and 3.2 W, respectively, which is suitable for power-limited small satellite systems. Algorithms and parameters of each block are optimized aiming at reducing hardware resource utilization. A low-density parity-check code constructed by the Euclidean geometry method is adopted as the channel code for forward error correction. Implementations of the synchronization, demodulation, and decoding algorithms are optimized for hardware efficiency. The low-power SDR designs are implemented on an FPGA-based experimental platform and successful demonstrated by over-the-air transmissions.