Efficient analog layout prototyping by layout reuse with routing preservation

To strive for better circuit performance on analog design, layout generation heavily relies on experienced analog designers' effort. Other than general analog constraints such as symmetry and wire-matching are commonly embraced in many proposed works, analog circuit performance is also sensitive to routing behavior. This paper presents a CDT-based layout extraction to preserve routing behavior of the reference layout. Furthermore, a generalized layout prototyping methodology is proposed based on the layout extraction to achieve routing reuse. The proposed layout prototyping is applied to a variable-gain amplifier and a folded-cascode operational amplifier for both migration and prototypes generation. Experimental results show that our approach effectively reduces design cycle time and simultaneously produces reasonable performance.

[1]  C.-J. Richard Shi,et al.  Multilevel symmetry-constraint generation for retargeting large analog layouts , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Yao-Wen Chang,et al.  Analog Placement Based on Symmetry-Island Formulation , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Chris C. N. Chu,et al.  DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Alberto L. Sangiovanni-Vincentelli,et al.  Constraint-based channel routing for analog and mixed analog/digital circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[5]  Nils J. Nilsson,et al.  A Formal Basis for the Heuristic Determination of Minimum Cost Paths , 1968, IEEE Trans. Syst. Sci. Cybern..

[6]  Robert K. Brayton,et al.  Fishbone: a block-level placement and routing scheme , 2003, ISPD '03.

[7]  C. Y. Lee.  An Algorithm for Path Connections and Its Applications , 1961, IRE Trans. Electron. Comput..

[8]  Hung-Ming Chen,et al.  Configurable analog routing methodology via technology and design constraint unification , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[9]  Rob A. Rutenbar,et al.  KOAN/ANAGRAM II: new tools for device-level analog placement and routing , 1991 .

[10]  C.-J. Richard Shi,et al.  Correct-by-construction layout-centric retargeting of large analog designs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[11]  D. T. Lee,et al.  Critical area computation via Voronoi diagrams , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Chien-Hung Chen,et al.  Fast analog layout prototyping for nanometer design migration , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[13]  Tsung-Yi Ho,et al.  Performance-driven analog placement considering monotonic current paths , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[14]  Muhammet Mustafa Ozdal,et al.  Exact route matching algorithms for analog and mixed signal integrated circuits , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[15]  Jonathan Richard Shewchuk,et al.  Delaunay refinement algorithms for triangular mesh generation , 2002, Comput. Geom..

[16]  Yanheng Zhang,et al.  GDRouter: Interleaved global routing and detailed routing for ultimate routability , 2012, DAC Design Automation Conference 2012.

[17]  Jai-Ming Lin,et al.  Routability-driven placement algorithm for analog integrated circuits , 2012, ISPD '12.

[18]  Rob A. Rutenbar,et al.  Automation of IC Layout with Analog Constraints , 2002 .

[19]  Yao-Wen Chang,et al.  Non-uniform multilevel analog routing with matching constraints , 2012, DAC Design Automation Conference 2012.

[20]  Evangeline F. Y. Young,et al.  Practical placement and routing techniques for analog circuit designs , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[21]  Hazem M. Abbas,et al.  Chameleon ART: a non-optimization based analog design migration framework , 2006, 2006 43rd ACM/IEEE Design Automation Conference.