IN-CHANNEL MISROUTING SUPPRESSION TECHNIQUE FOR DEFLECTION-ROUTED NETWORKS ON CHIP

Deflection routing, where port-contentions in routers are resolved by intentionally misrouting some of packets along unwanted directions instead of storing them, has been proposed as a promising approach for improving power and area efficiency of large-scale networks on chip (NoCs). However, at high network load, when packets are misrouted more frequently, the cost and energy benefits of this simple routing scheme are offset by the performance degradation. To address this problem, we propose a technique that uses small in-channel buffers to capture some of deflected packets before they take a misrouting hop. The captured packets are then looped-back to the routers where they suffered deflection and routed again. To improve the efficiency of this in-channel misrouting suppression scheme we also slightly modify the routing function of the deflection router by restricting the choice of productive directions for misrouted packets. Evaluations on synthetic traffic patterns show that the proposed misrouting suppression mechanism yields an improvement of 36.2% in network saturation throughput when implemented into the conventional deflection-routed network.

[1]  Kevin Kai-Wei Chang,et al.  MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[2]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[3]  Nanning Zheng,et al.  LDBR: Low-deflection bufferless router for cost-sensitive network-on-chip design , 2014, Microprocess. Microsystems.

[4]  Onur Mutlu,et al.  A case for bufferless routing in on-chip networks , 2009, ISCA '09.

[5]  William J. Dally.  Virtual-channel flow control , 1990, ISCA '90.

[6]  Milica D. Jovanovic,et al.  Dual-mode inter-router communication channel for deflection-routed networks-on-chip , 2015, The Journal of Supercomputing.

[7]  Natalie D. Enright Jerger,et al.  SCARAB: A single cycle adaptive routing and bufferless network , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[8]  John Jose,et al.  DeBAR: Deflection based adaptive router with minimal buffering , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[9]  Niraj K. Jha,et al.  A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS , 2007, ICCD.

[10]  Martin Radetzki,et al.  Fault-tolerant architecture and deflection routing for degradable NoC switches , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[11]  Chris Fallin,et al.  CHIPPER: A low-complexity bufferless deflection router , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[12]  Axel Jantsch,et al.  Evaluation of deflection routing on various NoC topologies , 2011, 2011 9th IEEE International Conference on ASIC.

[13]  George Michelogiannakis,et al.  Evaluating Bufferless Flow Control for On-chip Networks , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.