Parallel Test Scheduling of 3D Stacked SoCs with Temperature and Time Constraints

Today’s VLSI circuits are very compact and complex designs. As the advancements made are very fast with cut throat competitions from various manufacturers, they are likely to have more defects and faults. This requires a proper testing process to be adopted for all products. Testing is a process which has to be done on all pieces of products. At the same time it requires a low cost, highly efficient method to be adopted. Fault coverage should also be maximized for ensuring fast and efficient work. The technology is also undergoing fast transitions. System on Chip is a design paradigm which involves integration of entire system onto a single chip. It can be a RAM, DRAM, CPU, UDL, analog , digital, A/D or D/A converters needed for any particular requirement. In this paper we have worked on test scheduling of 3D SoCs with thermal and time constraints. The circuits used have been built using benchmark SoC circuits. They have been piled on top of each other to build two, three and four stack circuits. The method has been compared with the sequential method of testing. The method proposed in this work shows good thermal response and elimination of hotspots.

[1]  Nilanjan Mukherjee,et al.  Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm , 2002, Proceedings. International Test Conference.

[2]  Kewal K. Saluja,et al.  TEST SCHEDULING IN TESTABLE VLSI CIRCUITS , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

[3]  Erik Jan Marinissen,et al.  Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs , 2002, DAC '02.

[4]  Erik Jan Marinissen,et al.  Testing TSV-based three-dimensional stacked ICs , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[5]  Henryk Krawczyk,et al.  An Approximation Algorithm for Diagnostic Test Scheduling in Multicomputer Systems , 1985, IEEE Transactions on Computers.

[6]  Krishnendu Chakrabarty,et al.  Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling , 2006, 2006 IEEE International Test Conference.

[7]  Qiang Xu,et al.  Test architecture design and optimization for three-dimensional SoCs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[8]  Xiaoxia Wu,et al.  Test-access mechanism optimization for core-based three-dimensional SOCs , 2010, Microelectron. J..

[9]  Bashir M. Al-Hashimi,et al.  Power constrained test scheduling using power profile manipulation , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[10]  Erik Jan Marinissen,et al.  A set of benchmarks for modular testing of SOCs , 2002, Proceedings. International Test Conference.

[11]  Erik Jan Marinissen,et al.  On using rectangle packing for SOC wrapper/TAM co-optimization , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[12]  M. A. Breuer,et al.  Test schedules for VLSI circuits having built-in test hardware , 1987 .

[13]  Wang-Dauh Tseng.  Power-Oriented Test Scheduling for SOCs , 2006 .

[14]  Chunsheng Liu,et al.  Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[15]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[16]  Xiaoxia Wu,et al.  Test-access mechanism optimization for core-based three-dimensional SOCs , 2008, 2008 IEEE International Conference on Computer Design.

[17]  Petru Eles,et al.  Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[18]  Vishwani D. Agrawal,et al.  Scheduling tests for VLSI systems under power constraints , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Erik Jan Marinissen,et al.  Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip , 2003, IEEE Trans. Computers.

[20]  Vishwani D. Agrawal,et al.  Power constraint scheduling of tests , 1994, Proceedings of 7th International Conference on VLSI Design.