A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion

This paper presents a 25-Gb/s low-power Clock and Data Recovery (CDR) with an active-stabilizing Current Mode Logic (CML)-CMOS conversion circuit for an optical receiver. To reduce power consumption, the proposed receiver uses CMOS topology in the CDR stage. This architecture needs signal level conversion from CML to CMOS, but the conversion circuit is difficult to stabilize. We solve this problem by feedforwarding the LA output offset voltage to CML-CMOS converter. The feedforwarding suppresses the degradation of the eye-opening of the CML-CMOS conversion by 40%. Additionally, in the CDR, we reduce power consumption by more than 30% by using Transmission-Gate Delay Flip-flop (TG D-FF) instead of conventional C2MOS D-FF. The measured power consumption of the proposed receiver is 19.3 mW at 25-Gb/s operation, 80% lower than that of a receiver with CML-CDR.