Evaluation Of Compact FPGA Implementations For All SHA-3 Finalists

Secure cryptographic hash functions are core components in many applications like challenge-response authentication systems or digital signature schemes. Many of these applications are used in cost-sensitive markets and thus low budget implementations of such components are very important. In the present paper, we evalute the finalists of the SHA-3 competition, started by the National Institute of Standards and Technology (NIST). This work adds new valuable data to the competition, by providing architectures for compact implementations of all finalists. We focus on area-efficiency and therefore we do not rank the candidates by absolute throughput, but rather by the area and the throughput-area ratio. The results hint that Grøstl is the best overall performer for compact implementations, if the throughput-area ratio is most important. The following candidates are JH, Keccak and BLAKE, which are close together, while the current Skein architecture trails behind. The area ranking changes the results and puts JH on the top, followed by one of the BLAKE implementations, Grøstl, Keccak and Skein.

[1]  Kris Gaj,et al.  Very Compact FPGA Implementation of the AES Algorithm , 2003, CHES.

[2]  David Canright,et al.  A Very Compact S-Box for AES , 2005, CHES.

[3]  Xiaoyun Wang,et al.  Finding Collisions in the Full SHA-1 , 2005, CRYPTO.

[4]  J. Leasure,et al.  Announcing request for candidate algorithm nominations for a new cryptographic hash algorithm (SHA-3 , 2007 .

[5]  Palash Sarkar,et al.  New Collision Attacks against Up to 24-Step SHA-2 , 2008, INDOCRYPT.

[6]  Stefan Lucks,et al.  The Skein Hash Function Family , 2009 .

[7]  Kyoji Shibutani,et al.  Preimage Attacks on Reduced Tiger and SHA-2 , 2009, FSE.

[8]  Willi Meier,et al.  SHA-3 proposal BLAKE , 2009 .

[9]  Hongjun Wu,et al.  The Hash Function JH , 2009 .

[10]  Florian Mendel,et al.  Symmetric Cryptography , 2009 .

[11]  Steffen Reith,et al.  On FPGA-Based Implementations of the SHA-3 Candidate Grøstl , 2010, 2010 International Conference on Reconfigurable Computing and FPGAs.

[12]  William P. Marnane,et al.  FPGA Implementations of the Round Two SHA-3 Candidates , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[13]  Eiji Okamoto,et al.  Compact implementations of BLAKE-32 and BLAKE-64 on FPGA , 2010, 2010 International Conference on Field-Programmable Technology.

[14]  Steffen Reith,et al.  On FPGA-based implementations of Gröstl , 2010, IACR Cryptol. ePrint Arch..

[15]  Kris Gaj,et al.  ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[16]  Ekawat Homsirikamol,et al.  Comparing Hardware Performance of Round 3 SHA-3 Candidates using Multiple Hardware Architectures in Xilinx and Altera FPGAs , 2011 .

[17]  Bernhard Jungk,et al.  Area-Efficient FPGA Implementations of the SHA-3 Finalists , 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

[18]  François Durvaux,et al.  Compact FPGA Implementations of the Five SHA-3 Finalists , 2011, CARDIS.

[19]  John Pham,et al.  Lightweight Implementations of SHA-3 Candidates on FPGAs , 2011, INDOCRYPT.