Very high SFDR interpolation filters for software radio
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[1] Vijay K. Jain,et al. Hardware implementation of a nonlinear processor , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[2] Vijay K. Jain,et al. Rapid System Prototyping for High Performance Reconfigurable Computing , 2000, Des. Autom. Embed. Syst..
[3] V. K. Jain,et al. Floating-point nonlinear DSP coprocessor cell-two cycle chip , 1996, VLSI Signal Processing, IX.
[4] V. K. Jain,et al. Nonlinear DSP coprocessor cells-one and two cycle chips , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
[5] Vijay K. Jain. Mapping a high-speed wireless communication function to the reconfigurable J-platform , 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).
[6] V. K. Jain,et al. Image processing using a universal nonlinear cell , 1994, Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI).