Design of an Ultra-Low Power CT ΣΔ A/D Modulator in 65 nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation

A high performance, ultra-low power, fully differen- tial 2 nd -order continuous-time �� analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182 nA from a 1.2 V power supply, meeting the ultra- low power requirement of the cardiac pacemaker applications. A 65 nm CMOS technology is employed to implement the �� modulator. The modulator achieves a simulated SNR of 53.8 dB over a 400 Hz signal bandwidth, with 32 KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45 × 0.50mm 2 .