High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures
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Denis Flandre | Marcelo Antonio Pavanello | Jean-Pierre Raskin | Joao Antonio Martino | D. Flandre | J. Raskin | J. Martino | M. Pavanello
[1] Denis Flandre,et al. Subthreshold slope of long-channel accumulation-mode p-channel SOI MOSFETs , 1994 .
[2] D. Flandre,et al. Measurement of threshold voltages of thin-film accumulation-mode PMOS/SOI transistors , 1991, IEEE Electron Device Letters.
[3] Denis Flandre,et al. Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects , 2000 .
[4] Yuan Taur,et al. Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.
[5] Seiki Ogura,et al. A new asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half-micrometer n-MOSFET design for reliability and performance , 1989 .
[6] Denis Flandre,et al. Analog performance and application of graded-channel fully depleted SOI MOSFETs , 2000 .
[7] Chung-Yu Wu,et al. A new experimental method to determine the saturation voltage of a small-geometry MOSFET , 1988 .
[8] Denis Flandre,et al. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics , 1999 .
[9] Denis Flandre,et al. Influence of device engineering on the analog and RF performances of SOI MOSFETs , 2003 .
[10] Denis Flandre,et al. Gate-all-around OTA's for rad-hard and high-temperature analog applications , 1999 .
[11] J. Colinge,et al. Silicon-on-insulator 'gate-all-around device' , 1990, International Technical Digest on Electron Devices.
[12] Denis Flandre,et al. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs , 2002 .
[13] Denis Flandre,et al. Analog circuit design using graded-channel SOI nMOSFETs , 2001, Symposium on Integrated Circuits and Systems Design.
[14] James E. Murguia,et al. Use of focused-ion-beam and modeling to optimize submicron MOSFET characteristics , 1998 .
[15] Denis Flandre,et al. Comparison of SOI versus bulk performances of CMOS micropower single-stage OTAs , 1994 .
[16] Chenming Hu,et al. A folded-channel MOSFET for deep-sub-tenth micron era , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[17] L. Rubin. Low Temperature Electronics: Physics, Devices, Circuits, and Applications , 2002 .
[18] Atsushi Hori,et al. A high performance 0.1 /spl mu/m MOSFET with asymmetric channel profile , 1995, Proceedings of International Electron Devices Meeting.
[19] Denis Flandre,et al. Impact of the Graded-Channel Architecture on Double Gate Transistors for High-Performance Analog Applications , 2003 .
[20] Eddy Simoen,et al. Simple method for the determination of the interface trap density at 77 K in fully depleted accumulation mode SOI MOSFETs , 1993 .
[21] H.V. Deshpande,et al. Analog device design for low power mixed mode applications in deep submicron CMOS technology , 2001, IEEE Electron Device Letters.