Redefining and testing interconnect faults in Mesh NoCs

An extended fault model and novel strategy to tackle interconnect faults in network-on-chips are proposed. Short faults between distinct channels are considered in a cost-effective test sequence for mesh NoC topologies based on XY routing.

[1]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[2]  Partha Pratim Pande,et al.  Methodologies and algorithms for testing switch-based NoC interconnects , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[3]  R. Ubar,et al.  An External Test Approach for Network-on-a-Chip Switches , 2006, 2006 15th Asian Test Symposium.

[4]  Jin HoAhn,et al.  Test Scheduling of NoC-Based SoCs Using Multiple Test Clocks , 2006 .

[5]  Altamiro Amadeu Susin,et al.  RASoC: a router soft-core for networks-on-chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[6]  Fernando Gehm Moraes,et al.  HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..

[7]  Alexandre M. Amory,et al.  A scalable test strategy for network-on-chip routers , 2005, IEEE International Conference on Test, 2005..

[8]  Partha Pratim Pande,et al.  Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[9]  Chita R. Das,et al.  A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[10]  Wu-Tung Cheng,et al.  Diagnosis for wiring interconnects , 1990, Proceedings. International Test Conference 1990.

[11]  Altamiro Amadeu Susin,et al.  SoCIN: a parametric and scalable network-on-chip , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[12]  Artur Jutman,et al.  At-speed on-chip diagnosis of board-level interconnect faults , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[13]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[14]  Charles E. Stroud.  A Designer's Guide to Built-In Self-Test , 2002 .

[15]  Jong-Sun Kim,et al.  On-chip network based embedded core testing , 2004, IEEE International SOC Conference, 2004. Proceedings..

[16]  Spyros Tragoudas,et al.  Interconnect testing for networks on chips , 2006, 24th IEEE VLSI Test Symposium.

[17]  Kees G. W. Goossens,et al.  Bringing communication networks on a chip: test and verification implications , 2003, IEEE Commun. Mag..

[18]  Luca Benini,et al.  Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[19]  S. Kumar,et al.  Design issues and performance evaluation of mesh NoC with regions , 2005, 2005 NORCHIP.

[20]  Partha Pratim Pande,et al.  BIST for network-on-chip interconnect infrastructures , 2006, 24th IEEE VLSI Test Symposium.

[21]  Raimund Ubar,et al.  Off-Line Testing of Delay Faults in NoC Interconnects , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[22]  Luigi Carro,et al.  Reusing an on-chip network for the test of core-based systems , 2004, TODE.

[23]  William H. Kautz,et al.  Testing for Faults in Wiring Networks , 1974, IEEE Transactions on Computers.

[24]  Sujit Dey,et al.  Fault modeling and simulation for crosstalk in system-on-chip interconnects , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).