Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits

Due to current technology scaling trends, digital designs are becoming more sensitive to radiation-induced particle hits resulting from radioactivity decay and cosmic rays. A low-energy particle can flip the output of a gate, resulting in a soft error if it propagates to a circuit output. Thus, soft error tolerance has become an important criterion in digital system design. In this work, we propose a simulation-based approach to reduce the soft error probability of circuit failure in combinational logic circuits. The proposed method is based on maximizing the probability of logical masking when a soft error occurs. This maximization is done by extracting sub-circuits from an original multi-level circuit, and then re-synthesizing each extracted sub-circuit to increase fault masking against a single fault. We present a two-level synthesis scheme to maximize soft error masking on each extracted sub-circuit. This scheme provides a heuristic that finds the best set of cubes to cover the input patterns of an extracted sub-circuit. A Fast Extraction (FX) algorithm is used to enhance the area overhead of synthesized two-level sub-circuits. Experimental results on some MCNC combinational benchmarks show that, on average, a probability of circuit failure reduction of 32% is achieved compared to the original circuit. The average area overhead is 40% of the original circuit.

[1]  Kartik Mohanram,et al.  Low Cost Concurrent Error Masking Using Approximate Logic Circuits , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Diana Marculescu,et al.  Modeling and Optimization for Soft-Error Reliability of Sequential Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Mahmut T. Kandemir,et al.  Reliability-centric high-level synthesis , 2005, Design, Automation and Test in Europe.

[4]  Arthur F. Witulski,et al.  Impact of logic synthesis on soft error vulnerability using a 90-nm bulk CMOS digital cell library , 2011, 2011 Proceedings of IEEE Southeastcon.

[5]  Hao Chen,et al.  Reliability evaluation of logic circuits using probabilistic gate models , 2011, Microelectron. Reliab..

[6]  Robert K. Brayton,et al.  SAT-based complete don't-care computation for network optimization , 2005, Design, Automation and Test in Europe.

[7]  D. Sylvester,et al.  Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[8]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[9]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[10]  Aiman H. El-Maleh,et al.  A finite state machine based fault tolerance technique for sequential circuits , 2014, Microelectron. Reliab..

[11]  Abhijit Chatterjee,et al.  Analysis and optimization of nanometer CMOS circuits for soft-error tolerance , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[13]  Diana Marculescu,et al.  Circuit Reliability Analysis Using Symbolic Techniques , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Aiman H. El-Maleh,et al.  A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits , 2014, Microelectron. Reliab..

[15]  John P. Hayes,et al.  Introduction to Digital Logic Design , 1993 .

[16]  Vishwani D. Agrawal,et al.  Single Event Upset: An Embedded Tutorial , 2008, 21st International Conference on VLSI Design (VLSID 2008).

[17]  Sunil P. Khatri,et al.  A robust algorithm for approximate compatible observability don't care (CODC) computation , 2004, Proceedings. 41st Design Automation Conference, 2004..

[18]  Janusz Rajski,et al.  The testability-preserving concurrent decomposition and factorization of Boolean expressions , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Narayanan Vijaykrishnan,et al.  Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits , 2009, IEEE Transactions on Dependable and Secure Computing.

[20]  Y. Tosaka,et al.  Cosmic ray neutron-induced soft errors in sub-half micron CMOS circuits , 1997, IEEE Electron Device Letters.

[21]  Jianbo Gao,et al.  Toward hardware-redundant, fault-tolerant logic for nanoelectronics , 2005, IEEE Design & Test of Computers.

[22]  Sandeep K. Gupta,et al.  A new circuit simplification method for error tolerant applications , 2011, 2011 Design, Automation & Test in Europe.

[23]  Diana Marculescu,et al.  Soft error rate reduction using redundancy addition and removal , 2008, 2008 Asia and South Pacific Design Automation Conference.

[24]  B. L. Bhuva,et al.  Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty , 2013, IEEE Transactions on Nuclear Science.

[25]  Bashir M. Al-Hashimi,et al.  Defect-tolerant n2-transistor structure for reliable nanoelectronic designs , 2009, IET Comput. Digit. Tech..

[26]  Hao Chen,et al.  A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation , 2014, IEEE Transactions on Computers.

[27]  Mehdi Baradaran Tahoori,et al.  Efficient algorithms to accurately compute derating factors of digital circuits , 2012, Microelectron. Reliab..

[28]  Sanjukta Bhanja,et al.  Probabilistic Error Modeling for Nano-Domain Logic Circuits , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[29]  Malgorzata Marek-Sadowska Shih-Chieh Chang.  An Efficient Algorithm for Local Don't Care Sets Calculation , 1995, 32nd Design Automation Conference.

[30]  David Blaauw,et al.  Logic SER reduction through flip flop redesign , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[31]  N. Seifert,et al.  Robust system design with built-in soft-error resilience , 2005, Computer.

[32]  Nur A. Touba,et al.  Partial error masking to reduce soft error failure rate in logic circuits , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[33]  W. H. Robinson,et al.  Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance Testing , 2013, IEEE Transactions on Nuclear Science.

[34]  Kartik Mohanram,et al.  Gate sizing to radiation harden combinational logic , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[35]  L.W. Massengill,et al.  Reducing Soft Error Rate in Logic Circuits Through Approximate Logic Functions , 2006, IEEE Transactions on Nuclear Science.

[36]  Kartik Mohanram,et al.  Reliability-driven don't care assignment for logic synthesis , 2011, 2011 Design, Automation & Test in Europe.

[37]  John P. Hayes,et al.  Enhancing design robustness with reliability-aware resynthesis and logic simulation , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[38]  Fabrizio Lombardi,et al.  Analysis of Error Masking and Restoring Properties of Sequential Circuits , 2013, IEEE Transactions on Computers.

[39]  David J. Lilja,et al.  Fault tolerance for nanotechnology devices at the bit and module levels with history index of correct computation , 2011, IET Comput. Digit. Tech..

[40]  Yiorgos Makris,et al.  Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires , 2008, IEEE Transactions on Reliability.