HPC application in 3D parameter extraction and hard IP migration for DSM IC design
暂无分享,去创建一个
[1] Makuhari Messe. Proceedings of the ASP-DAC '97 , 1997 .
[2] Zinaida V. Apanovich,et al. Top-down approach to technology migration for full-custom mask layouts , 1998, Proceedings Eleventh International Conference on VLSI Design.
[3] Akira Onozawa,et al. Post-layout optimization of power and timing for ECL LSIs , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.
[4] Massoud Pedram. Logical-physical co-design for deep submicron circuits: challenges and solutions , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.
[5] Malgorzata Marek-Sadowska,et al. Post-layout Logic Restructuring For Performance Optimization , 1997, Proceedings of the 34th Design Automation Conference.