The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding- gate field-effect transistor and circuit
暂无分享,去创建一个
[1] J. Bokor,et al. Sensitivity of double-gate and FinFETDevices to process variations , 2003 .
[2] R. Chau. Benchmarking nanotechnology for high-performance and low-power logic transistor applications , 2004 .
[3] Shao-Ming Yu,et al. A Coupled Simulation and Optimization Approach to Nanodevice Fabrication with Minimization of Electrical Characteristics Fluctuation , 2006 .
[4] Chenming Hu,et al. Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[5] Y. Yeo,et al. 25 nm CMOS Omega FETs , 2002, Digest. International Electron Devices Meeting,.
[6] Yiming Li,et al. A Practical Implementation of Parallel Dynamic Load Balancing for Adaptive Computing in VLSI Device Simulation , 2002, Engineering with Computers.
[7] Chih-Hong Hwang,et al. Large‐scale “atomistic” approach to discrete‐dopant‐induced characteristic fluctuations in silicon nanowire transistors , 2008 .
[8] Yiming Li,et al. Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors , 2004 .
[9] Yiming Li,et al. A Comparative Study of Electrical Characteristic on Sub-10-nm Double-Gate MOSFETs , 2005, IEEE Transactions on Nanotechnology.
[10] Shao-Ming Yu,et al. Comparison of Random-Dopant-Induced Threshold Voltage Fluctuation in Nanoscale Single-, Double-, and Surrounding-Gate Field-Effect Transistors , 2005 .
[11] Massimo V. Fischetti,et al. Scaling MOSFETs to the Limit: A Physicists's Perspective , 2003 .
[12] M.S. Islam,et al. Noise in Silicon Nanowires , 2006, IEEE Transactions on Nanotechnology.
[13] Shao-Ming Yu,et al. Discrete Dopant Fluctuated 20nm/15nm-Gate Planar CMOS , 2007, 2007 IEEE Symposium on VLSI Technology.
[14] M. Rudan,et al. Design Considerations and Comparative Investigation of Ultra-Thin SOI, Double-Gate and Cylindrical Nanowire FETs , 2006, 2006 European Solid-State Device Research Conference.
[15] Shao-Ming Yu,et al. A parallel adaptive finite volume method for nanoscale double-gate MOSFETs simulation , 2005 .
[16] J. Colinge,et al. Silicon-on-insulator 'gate-all-around device' , 1990, International Technical Digest on Electron Devices.
[17] A. Lazaro,et al. RF and Noise Performance of Multiple-Gate SOI MOSFETs , 2006, 2006 European Microwave Integrated Circuits Conference.
[18] Ting-wei Tang,et al. Discretization Scheme for the Density-Gradient Equation and Effect of Boundary Conditions , 2002 .
[19] J. Plummer,et al. Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's , 1997, IEEE Electron Device Letters.
[20] Chih-Hong Hwang,et al. Electrical characteristic fluctuations in 16 nm bulk-FinFET devices , 2007 .
[21] Ru Huang,et al. Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation , 2007, IEEE Transactions on Electron Devices.
[22] Shao-Ming Yu,et al. Discrete Dopant Fluctuations in 20-nm/15-nm-Gate Planar CMOS , 2008, IEEE Transactions on Electron Devices.
[23] Chih-Hong Hwang,et al. Discrete-dopant-induced characteristic fluctuations in 16nm multiple-gate silicon-on-insulator devices , 2007 .
[24] Chih-Hong Hwang,et al. High-Frequency Characteristic Fluctuations of Nano-MOSFET Circuit Induced by Random Dopants , 2008, IEEE Transactions on Microwave Theory and Techniques.
[25] S. Datta,et al. Silicon nano-transistors and breaking the 10 nm physical gate length barrier , 2003, 61st Device Research Conference. Conference Digest (Cat. No.03TH8663).
[26] Jean-Pierre Colinge,et al. Multiple-gate SOI MOSFETs: device design guidelines , 2002 .
[27] Yiming Li,et al. Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices , 2006, IEEE Custom Integrated Circuits Conference 2006.
[28] Chenming Hu,et al. 5nm-gate nanowire FinFET , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
[29] Z. Ren,et al. Simulation of nanoscale MOSFETs: a scattering theory interpretation , 2000 .
[30] Yiming Li,et al. Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs , 2005 .
[31] Denis Flandre,et al. Gate-all-around OTA's for rad-hard and high-temperature analog applications , 1999 .
[32] Shinji Odanaka,et al. Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[33] Bin Yu,et al. FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.
[34] S.C. Rustagi,et al. CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach , 2007, IEEE Electron Device Letters.
[35] Chih-Hong Hwang,et al. Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors , 2007, 2007 7th IEEE Conference on Nanotechnology (IEEE NANO).
[36] Yiming Li,et al. A novel parallel adaptive Monte Carlo method for nonlinear Poisson equation in semiconductor devices , 2003, Math. Comput. Simul..
[37] Siegfried Selberherr,et al. Mixed-mode device simulation , 2000 .
[38] Yiming Li,et al. DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit , 2009 .
[39] M. Ancona,et al. Macroscopic physics of the silicon inversion layer. , 1987, Physical review. B, Condensed matter.
[40] Frank Schwierz,et al. On the suitability of DD and HD models for the simulation of nanometer double-gate MOSFETs , 2003 .