Dynamic partial reconfigurable Viterbi decoder for wireless standards

In this paper, a high speed and low power runtime dynamically reconfigurable Viterbi decoder architecture with constraint lengths 3-7 with different code rates is proposed for different wireless standards. The proposed architecture uses an improved modular implementation of Add Compare Select (ACS) and Trace back units to obtain high speed. With a throughput of 81Mbps, the architecture is suitable for use in receivers of 802.11a wireless local area network, 3G cellular code division multiple access environments, UMTS and EDGE. The proposed architecture gives high performance without any pipelining or parallelism in ACS and shows at least 13% throughput and 5x power improvement over the reported architectures. To verify the efficacy of this dynamic partial reconfigurable (DPR) Viterbi decoder method, a conventional multiplexer based reconfigurable architecture was designed and tested. DPR based technique shows 27% of resource saving and the reconfiguration time is reduced about 1/9 compared to the static reconfiguration.

[1]  Pisana Placidi,et al.  A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver , 2008, Integr..

[2]  J.R. Cavallaro,et al.  A reconfigurable Viterbi decoder architecture , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[3]  R. Cumplido,et al.  A Runtime Reconfigurable Architecture for Viterbi Decoding , 2006, 2006 3rd International Conference on Electrical and Electronics Engineering.

[4]  Dennis Goeckel,et al.  A reconfigurable, power-efficient adaptive Viterbi decoder , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Eric McDonald.  Runtime FPGA Partial Reconfiguration , 2008, 2008 IEEE Aerospace Conference.

[6]  Khaled Shehata,et al.  Design and Implementation of Low-Power Viterbi Decoder for Software-Defined WiMAX Receiver , 2009 .

[7]  M. Omair Ahmad,et al.  A low-power systolic array-based adaptive Viterbi decoder and its FPGA implementation , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[8]  Tae-Jin Kim,et al.  High performance Viterbi decoder using modified register exchange methods , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[9]  Salwa H. El-Ramly,et al.  FPGA implementation of a reconfigurable Viterbi decoder for WiMAX receiver , 2009, 2009 International Conference on Microelectronics - ICM.

[10]  Andrew J. Viterbi,et al.  Error bounds for convolutional codes and an asymptotically optimum decoding algorithm , 1967, IEEE Trans. Inf. Theory.

[11]  Sangsung Choi,et al.  A Two-Stage Radix-4 Viterbi Decoder for Multiband OFDM UWB Systems , 2008 .

[12]  M. Omair Ahmad,et al.  FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Y.S. Rao,et al.  High speed area efficient configurable Viterbi Decoder for WiFi and WiMAX systems , 2007, 2007 International Conference on Intelligent and Advanced Systems.

[14]  T. Sansaloni,et al.  Efficient mapping on FPGA of a Viterbi decoder for wireless LANs , 2005, IEEE Workshop on Signal Processing Systems Design and Implementation, 2005..

[15]  Joseph R. Cavallaro,et al.  Viturbo: a reconfigurable architecture for Viterbi and turbo decoding , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..

[16]  Rizwan Rasheed.  Reconfigurable Viterbi decoder for mobile platform , 2005 .

[17]  M. Santhi,et al.  Synchronous pipelined two-stage radix-4 200Mbps MB-OFDM UWB Viterbi decoder on FPGA , 2009, 2009 International SoC Design Conference (ISOCC).

[18]  Dennis Goeckel,et al.  A dynamically reconfigurable adaptive viterbi decoder , 2002, FPGA '02.