Novel Hardware Algorithms for Row-Parallel Integral Image Calculation

The integral image is an intermediate image representation that allows rapid calculation of rectangular features at constant speed, irrespective of filter size, and is particularly useful for multi-scale computer vision algorithms like Speeded-Up Robust Features (SURF). Although calculation of the integral image involves simple addition operations, the total number of operations is significant due to the generally large size of image data. Recursive equations allow considerable reduction in the required number of addition operations but require calculation of the integral image in a serial fashion. This is generally not desirable for real-time embedded vision systems with strict time limitations and low-powered but parallel hardware resources. With the objective of minimizing the hardware resources involved, this paper proposes two novel hardware algorithms based on decomposition of these recursive equations, allowing calculation of up to four integral image values in a row-parallel way with out significantly increasing the number of addition operations.

[1]  Paul A. Viola,et al.  Rapid object detection using a boosted cascade of simple features , 2001, Proceedings of the 2001 IEEE Computer Society Conference on Computer Vision and Pattern Recognition. CVPR 2001.

[2]  Ming Yang,et al.  Face detection for automatic exposure control in handheld camera , 2006, Fourth IEEE International Conference on Computer Vision Systems (ICVS'06).

[3]  Luc Van Gool,et al.  Speeded-Up Robust Features (SURF) , 2008, Comput. Vis. Image Underst..

[4]  Narayanan Vijaykrishnan,et al.  A parallel architecture for hardware face detection , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[5]  B. Kisacanin,et al.  Integral Image Optimizations for Embedded Vision Applications , 2008, 2008 IEEE Southwest Symposium on Image Analysis and Interpretation.

[6]  Franklin C. Crow,et al.  Summed-area tables for texture mapping , 1984, SIGGRAPH.

[7]  Tsuhan Chen,et al.  Proposed FPGA Hardware Architecture for High Frame Rate (≫100 fps) Face Detection Using Feature Cascade Classifiers , 2007, 2007 First IEEE International Conference on Biometrics: Theory, Applications, and Systems.

[8]  Ryan Kastner,et al.  Fpga-based face detection system using Haar classifiers , 2009, FPGA '09.

[9]  Yu Wei,et al.  FPGA implementation of AdaBoost algorithm for detection of face biometrics , 2004, IEEE International Workshop on Biomedical Circuits and Systems, 2004..

[10]  Radu Marculescu,et al.  Communication-Aware Face Detection Using Noc Architecture , 2008, ICVS.