Algorithm for post global routing RLC crosstalk avoidance

Crosstalk has become one of the most critical concerns for a DSM router. In this paper, we propose an efficient algorithm for RLC crosstalk avoidance between global routing and detailed routing. This algorithm integrates several intermediate resource assignment operations as a whole, so that the traditionally separated design stages can cooperate to achieve the best result. Besides, congestion, vias and other such factors are also considered. Experimental results show that our approach can reduce RLC coupling effectively without disturbance on completion ratio.

[1]  William Nicholls,et al.  Track assignment: a desirable intermediate step between global routing and detailed routing , 2002, ICCAD 2002.

[2]  C. L. Liu,et al.  Minimum crosstalk channel routing , 1993, ICCAD.

[3]  C. L. Liu,et al.  Minimum crosstalk switchbox routing , 1994, ICCAD.

[4]  Yici Cai,et al.  Layer assignment algorithm for RLC crosstalk minimization , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[5]  Min Zhao,et al.  Layer assignment for crosstalk risk minimization , 2004 .

[6]  Carl Sechen,et al.  Timing- and crosstalk-driven area routing , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Rob A. Rutenbar,et al.  Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution , 2000, ISPD '00.

[8]  Yici Cai,et al.  Crosstalk driven routing resource assignment , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[9]  Yu Cao,et al.  RLC signal integrity analysis of high-speed global interconnects [CMOS] , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[10]  Rajendran Panda,et al.  Early probabilistic noise estimation for capacitively coupled interconnects , 2002, SLIP '02.

[11]  C. L. Liu,et al.  Minimum crosstalk channel routing , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..