A Design of Highly Stable and Low-Power SRAM Cell

A novel architecture of low power and highly stable SRAM cell has been proposed in this paper. The proposed design contains a voltage source (VS). This voltage source minimizes the swing voltage required for switching activity. Swing voltage reduction controls the dynamic power consumption at high speed. One NMOS transistor is used to isolate the direct path between bit line and data storage points and increases the external noise tolerance level. Power consumptions at various frequencies and static noise margins of the proposed model are noted down and the comparison is made with the other reported SRAM cell designs. 45 nm CMOS technology and Microwind 3.1 software tool are used for circuit simulation.

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